A Study on Physical Interconnect Design in 3D ICs Using Through Silicon Vias

• Project/Area Number: 26330057
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Computer system
• Research Institution: Hirosaki University
• Principal Investigator: Kurokawa Atsushi 弘前大学, 理工学研究科, 教授 (80610592)
• Project Period (FY): 2014-04-01 – 2017-03-31
• Project Status: Completed (Fiscal Year 2016)
• Budget Amount: ¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000); Fiscal Year 2016: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000); Fiscal Year 2015: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000); Fiscal Year 2014: ¥2,470,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥570,000)
• Keywords: 三次元集積回路 / 貫通シリコンビア / クロック分配 / 熱解析 / 電源分配 / 容量抽出

Outline of Final Research Achievements

The summaries of research results are as follows. 1) Interconnect resistance, inductance and capacitance under various conditions in 3D ICs were analyzed by an electromagnetic solver, values of each RLC were clarified, and several capacitance equations were developed. 2) The propagation delay and crosstalk noise were analyzed with a circuit simulator, effect of substrate contacts on delay was clarified, and equations to easily get the delay and noise were developed. 3) A method to reduce clock skew among stacked chips by a clock distribution network with multiple source buffers was developed. 4) The power distribution network was modelled and the voltage drops were clarified by circuit simulations. 5) The thermal distribution in 3D ICs was clarified by a thermal conductivity analyzer and new cooling architectures using thermal sidewalls, interchip plates, and a bottom plate (thermal-SIB architectures) were developed.

Research Products

• [Journal Article] Signal Propagation Delay Model in Vertically Stacked Chips (2015)
  • Author(s): Nanako Niioka, Masayuki Watanabe, Masaaki Fukase, Masashi Imai, and Atsushi Kurokawa
  • Journal Title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Volume: E98.A Issue: 12 Pages: 2614-2624
  • DOI: 10.1587/transfun.E98.A.2614
  • NAID: 130005111976
  • ISSN: 0916-8508, 1745-1337
  • Peer Reviewed / Int'l Joint Research / Acknowledgement Compliant
• [Journal Article] インダクタンス逆行列を用いた三次元集積回路の貫通シリコンビア間結合容量抽出 (2015)
  • Author(s): 小林徹哉, 新岡七奈子, 深瀬政秋, 黒川敦
  • Journal Title: 電気学会 論文誌C Volume: ?
  • NAID: 130005086250
  • Peer Reviewed / Acknowledgement Compliant
• [Presentation] Cooling architectures using thermal sidewalls, interchip plates, and bottom plate for 3D ICs (2017)
  • Author(s): Kaoru Furumi, Masashi Imai, and Atsushi Kurokawa
  • Organizer: Proc. of the International Symposium on Quality Electronic Design
  • Place of Presentation: Santa Clara Convention Center, CA, USA
  • Year and Date: 2017-03-14
  • Int'l Joint Research
• [Presentation] 数百層積層メモリにおける各パラメータの温度への影響 (2017)
  • Author(s): 岡本慎太郎, 黒川敦
  • Organizer: 情報処理学会 東北支部研究会
  • Place of Presentation: 弘前大学
• [Presentation] チップ外周熱伝導壁による三次元集積回路の温度低減 (2016)
  • Author(s): 古見薫, 新岡七奈子, 岡本慎太郎, 今井雅, 黒川敦
  • Organizer: 電子情報通信学会 ソサエティ大会
  • Place of Presentation: 北海道大学
  • Year and Date: 2016-09-20
• [Presentation] 三次元集積回路の熱解析 (2016)
  • Author(s): 古見薫, 今井雅, 新岡七奈子, 黒川敦
  • Organizer: 電子情報通信学会 VLSI設計技術研究会
  • Place of Presentation: 青森県弘前市（弘前市立観光館）
  • Year and Date: 2016-06-16
• [Presentation] マルチソースバッファを用いた積層チップのクロック分配方法 (2016)
  • Author(s): 新岡七奈子, 今井雅, 古見薫, 黒川敦
  • Organizer: 電子情報通信学会 VLSI設計技術研究会
  • Place of Presentation: 青森県弘前市（弘前市立観光館）
  • Year and Date: 2016-06-16
• [Presentation] 積層チップの電源分配のモデリングと電圧降下の解析 (2016)
  • Author(s): 古見薫, 深瀬政秋, 新岡七奈子, 黒川敦
  • Organizer: 電子情報通信学会 総合大会
  • Place of Presentation: 福岡県福岡市（九州大学 伊都キャンパス）
  • Year and Date: 2016-03-16
• [Presentation] TSVベース3D-ICの垂直方向配線間結合容量の効率的な抽出方法 (2016)
  • Author(s): 小林徹哉, 新岡七奈子, 古見薫, 黒川敦
  • Organizer: 情報処理学会 東北支部研究会
  • Place of Presentation: 青森県弘前市（弘前大学）
  • Year and Date: 2016-02-19
• [Presentation] 3次元積層チップの熱解析と温度上昇抑制方法 (2016)
  • Author(s): 古見薫, 新岡七奈子, 黒川敦
  • Organizer: 情報処理学会 東北支部研究会
  • Place of Presentation: 青森県弘前市（弘前大学）
  • Year and Date: 2016-02-19
• [Presentation] Clock skew reduction for stacked chips using multiple source buffers (2015)
  • Author(s): Nanako Niioka, Masashi Imai, Masa-aki Fukase, Yuuki Miura, Kaoru Furumi, and Atsushi Kurokawa
  • Organizer: IEEE International Symposium on Communications and Information Technologies (ISCIT)
  • Place of Presentation: 奈良県奈良市（奈良県新公会堂）
  • Year and Date: 2015-10-09
  • Int'l Joint Research
• [Presentation] Thermal analysis with varying physical parameters in 3D ICs (2015)
  • Author(s): Kaoru Furumi, Masa-aki Fukase, Masashi Imai, Yuuki Miura, Nanako Niioka, and Atsushi Kurokawa
  • Organizer: 電気学会 電子・情報・システム部門大会
  • Place of Presentation: 長崎県長崎市（長崎大学）
  • Year and Date: 2015-08-26
• [Presentation] 三次元集積回路の伝搬遅延とクロストークノイズのモデリング (2015)
  • Author(s): 新岡七奈子, 深瀬政秋, 今井雅, 古見薫, 三浦祐輝, 黒川敦
  • Organizer: 電子情報通信学会 回路とシステムワークショップ
  • Place of Presentation: 兵庫県淡路市（淡路夢舞台国際会議場）
  • Year and Date: 2015-08-03
• [Presentation] ウィンドウベースL 逆行列によるTSV 間容量抽出 (2015)
  • Author(s): 小林徹哉, 今井雅, 深瀬政秋, 新岡七奈子, 黒川敦
  • Organizer: 電子情報通信学会 総合大会 講演論文集
  • Place of Presentation: 滋賀県草津市（立命館大学）
  • Year and Date: 2015-03-13
• [Presentation] An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs (2015)
  • Author(s): Masayuki Watanabe, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Masa-aki Fukase, Masashi Imai, and Atsushi Kurokawa
  • Organizer: Proc. of the International Symposium on Quality Electronic Design (ISQED)
  • Place of Presentation: サンタクララ、CA、USA
  • Year and Date: 2015-03-04
• [Presentation] Modeling of substrate contacts in TSV-based 3D ICs (2014)
  • Author(s): Masayuki Watanabe, Masa-aki Fukase, Masashi Imai, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, and Atsushi Kurokawa
  • Organizer: Proc. of the IEEE International Conference on 3D System Integration (3DIC)
  • Place of Presentation: キンセール、アイルランド
  • Year and Date: 2014-12-01
• [Presentation] Effect of substrate contacts on reducing crosstalk noise between TSVs (2014)
  • Author(s): Masayuki Watanabe, Rosely Karel, Nanako Niioka, Tetsuya Kobayashi, Masa-aki Fukase, Masashi Imai, and Atsushi Kurokawa
  • Organizer: Proc. of the IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)
  • Place of Presentation: 沖縄県石垣市
  • Year and Date: 2014-11-20
• [Presentation] Impact of on-chip interconnects on vertical signal propagation in 3D ICs (2014)
  • Author(s): Nanako Niioka, Masayuki Watanabe, Rosely Karel, Tetsuya Kobayashi, Masashi Imai, Masa-aki Fukase, and Atsushi Kurokawa
  • Organizer: Proc. of the IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)
  • Place of Presentation: 沖縄県石垣市
  • Year and Date: 2014-11-19
• [Presentation] インダクタンス逆行列を用いた三次元集積回路の貫通シリコンビア間結合容量抽出 (2014)
  • Author(s): 小林徹哉，新岡七奈子，深瀬政秋，黒川敦
  • Organizer: 電気学会 電子・情報・システム部門大会 講演論文集
  • Place of Presentation: 島根県松江市（島根大学）
  • Year and Date: 2014-09-03
• [Presentation] Substrate contact effect on TSV-to-TSV coupling (2014)
  • Author(s): Rosely Karel, Masa-aki Fukase, Masashi Imai, Nanako Niioka, Tetsuya Kobayashi, and Atsushi Kurokawa
  • Organizer: Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session)
  • Place of Presentation: 山形県米沢市(山形大学)
  • Year and Date: 2014-08-21
• [Presentation] Modeling and analysis of vertical interconnects in 3D ICs (2014)
  • Author(s): Nanako Niioka, Masashi Imai, Masa-aki Fukase, Rosely Karel, Tetsuya Kobayashi, and Atsushi Kurokawa
  • Organizer: Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session)
  • Place of Presentation: 山形県米沢市(山形大学)
  • Year and Date: 2014-08-21