| Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2016: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2015: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2014: ¥2,470,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥570,000)
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| Outline of Final Research Achievements |
The summaries of research results are as follows. 1) Interconnect resistance, inductance and capacitance under various conditions in 3D ICs were analyzed by an electromagnetic solver, values of each RLC were clarified, and several capacitance equations were developed. 2) The propagation delay and crosstalk noise were analyzed with a circuit simulator, effect of substrate contacts on delay was clarified, and equations to easily get the delay and noise were developed. 3) A method to reduce clock skew among stacked chips by a clock distribution network with multiple source buffers was developed. 4) The power distribution network was modelled and the voltage drops were clarified by circuit simulations. 5) The thermal distribution in 3D ICs was clarified by a thermal conductivity analyzer and new cooling architectures using thermal sidewalls, interchip plates, and a bottom plate (thermal-SIB architectures) were developed.
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