Design space exploration of highly energy efficient processors by fine-grain 3-D IC stacking technologies
| Project/Area Number |
26330058
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system
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| Research Institution | Yamagata University |
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Principal Investigator |
Tada Jubee 山形大学, 大学院理工学研究科, 助教 (30361273)
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| Co-Investigator(Kenkyū-buntansha) |
江川 隆輔 東北大学, サイバーサイエンスセンター, 准教授 (80374990)
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| Project Period (FY) |
2014-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2016: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2015: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2014: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
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| Keywords | 計算機アーキテクチャ / 三次元積層技術 / 集積回路設計 / 三次元積層型プロセッサ / VLSI設計 |
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| Outline of Final Research Achievements |
The purpose of this study is to realize a highly energy efficient processor by using a fine-grain 3-D IC stacking technology. At first, this study aimed to improve components of the processor by the 3-D IC stacking. As a result, it has been shown that the fine-grain partitioning of the components could improve the performance and the power consumption of the arithmetic unit. As compared to the 2-D implementation, the 3-D stacked arithmetic unit improved the performance up to 20%, and the power consumption up to 10%. Next, in order to improve the energy efficient of the computing node which has several floating-point units, the fine-grain circuit partitioning method was considered and the design space was explored. As a result, As compared to the 2-D implementation, the 3-D stacked computing node achieved an 8% performance improvement and an 18% power consumption reduction in maximum.
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Report
(4 results)
Research Products
(6 results)
