| Budget Amount *help |
¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2016: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2015: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2014: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
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| Outline of Final Research Achievements |
In this research, design of generic hardware for high speed classification in machine learning is proposed with providing flexible adaptability of its hardware organization. Specifically, a Support Vector Machine, which has inherent versatility for applications is accelerated by soft-cascade processing while maintaining its classification capability. Dimension of feature vectors and bit precision in calculation can be controlled without re-designing hardware. VLSI implementation is coordinated with the use of FPGA and 45nm technology to confirm the ability of adaptive reconfiguration. The designed FPGA and 45nm circuit attain 79VGA frames/7HD frames processing and 361VGA frames/35HD frames processing per second, respectively.
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