A Study on Network Intrusion Detection Hardware for Next-Generation High-Speed Ethernets
| Project/Area Number |
26330069
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system
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| Research Institution | Hiroshima City University |
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Principal Investigator |
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| Co-Investigator(Renkei-kenkyūsha) |
NAGAYAMA Shinobu 広島市立大学, 大学院情報科学研究科, 教授 (10405491)
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| Project Period (FY) |
2014-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2016: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2015: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2014: ¥2,600,000 (Direct Cost: ¥2,000,000、Indirect Cost: ¥600,000)
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| Keywords | ネットワーク侵入検知 / FPGA / 正規表現マッチング / 有限オートマトン / スクリーニング / 正規表現 / 非決定性有限オートマトン |
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| Outline of Final Research Achievements |
This research proposes a new structure of network intrusion detection systems for very high-speed internet, whose transmission rate is more than 40Ggps. In the proposed system, a dedicated circuit performs “screening” of input packets, and for suspicious packets which might contain “computer virus”, complete matching will be performed to determine they are in fact infected by a virus. The proposed system can achieve a high throughput while the circuit size can be reduced. Experimental results show the effectiveness of the proposed system.
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Report
(4 results)
Research Products
(5 results)
