| Budget Amount *help |
¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2016: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2015: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2014: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
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| Outline of Final Research Achievements |
With technology scaling, process, voltage, and temperature (PVT) variations and soft errors pose great challenges on integrated circuit designs. In this project, we conduct researches on in-situ error prediction for dependable low energy LSI designs, which is achieved by introducing the concept of prediction into LSI designs as a solution to the reliability problems of state-of-the-art integrated circuits. At first, a predication-based timing monitoring method called suspicious timing error prediction (STEP) was proposed for variation-resilient LSI designs. And then low power soft error tolerant latch designs have been developed to deal with the soft error problem. Finally, an in-situ prediction-based AVS method was proposed for energy minimization, which has been implemented and verified on a real large processor design.
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