Study of combinatorial and mathematical programming methods for high level synthesis
| Project/Area Number |
26420323
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Waseda University |
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Principal Investigator |
Yoshimura Takeshi 早稲田大学, 理工学術院(情報生産システム研究科・センター), 教授 (80367177)
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| Project Period (FY) |
2014-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2016: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2015: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2014: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
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| Keywords | 高位レベル合成 / 低消費電力化 / TSV / スケジューリング / 最適化 / VLSI / リソース割り当て / ポート割り当て問題 / 動的電力 / 漏れ電力 / 低消費電力 / ポート割り当て / アルゴリズム / Highlevel Synthesis / Scheduling / Binding / Low power |
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| Outline of Final Research Achievements |
The research on high level synthesis of system LSI were conducted. First, in the scheduling problem, a method based on a combination of mathematical programming and graph theory was proposed for the dynamic power optimization problem. For leakage power optimization problem, a method with the modifications of the above method and additional post-processing were proposed. In both problems, optimal solutions were obtained in most cases. In the port assignment problem, a method to avoid local optimal solutions considering sub-solution space and a method to reduce processing time were proposed. Optimal solutions were obtained for all the evaluation data. In the TSV assignment problem for three-dimensional LSI, a method to reduce the scale of the problem without sacrificing the solution quality was proposed based on a hierarchical design method. The CPU time was reduced to about 1/38 of the conventional methods.
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Report
(4 results)
Research Products
(16 results)
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[Journal Article] Leakage Power Aware Scheduling in High-Level Synthesis2014
Author(s)
Nan Wang, Song Chen, Cong Hao, Haoran Zhang, and Takeshi Yoshimura
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Journal Title
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume: E97.A
Issue: 4
Pages: 940-951
DOI
NAID
ISSN
0916-8508, 1745-1337
Related Report
Peer Reviewed / Open Access / Acknowledgement Compliant
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