| Project/Area Number |
26540022
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system
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| Research Institution | Kyushu University |
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Principal Investigator |
Inoue Koji 九州大学, システム情報科学研究科(研究院, 教授 (80341410)
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| Co-Investigator(Renkei-kenkyūsha) |
TANAKA Mitsumasa 名古屋大学, PhD登龍門推進室, 特任講師 (10377864)
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| Project Period (FY) |
2014-04-01 – 2016-03-31
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| Project Status |
Completed (Fiscal Year 2015)
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| Budget Amount *help |
¥3,510,000 (Direct Cost: ¥2,700,000、Indirect Cost: ¥810,000)
Fiscal Year 2015: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2014: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
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| Keywords | マイクロプロセッサ / 単一磁束量子回路 / 超伝導 / 高性能マイクロプロセッサ / 超伝導プロセッサ |
|---|
| Outline of Final Research Achievements |
CMOS microprocessors have been facing with a limitation of clock speeds because of increasing power consumption (i.e., power-wall problem). Single-Flux-Quantum (SFQ) devices and circuits are promising to solve the power-wall problem due to its ultra high-speed, low-power natures. This research explores the design space of microarchitecture to exploit the potential of SFQ devices and circuits. A novel architecture that supports SFQ-gate level fine-grained superpipelining with deep multithreading has been proposed. Our estimation presents that it has a potential to achieve 50X clock speed improvement compared to state-of-the-art CMOS microprocessors with several watt power comsumption. Since the estimation does not consider the speed and power overhead caused by layout, our future work is to implement the proposed microarchitecture with physical designs.
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