| Project/Area Number |
26630145
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tohoku University |
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Principal Investigator |
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| Project Period (FY) |
2014-04-01 – 2016-03-31
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| Project Status |
Completed (Fiscal Year 2015)
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| Budget Amount *help |
¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2015: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2014: ¥2,470,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥570,000)
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| Keywords | 細粒度リコンフィギャラブルVLSI / 多値差動対回路 / マイクロパケット転送 / 多値Ｘネット / 直接アロケーション / マルチプレクサロジック / ロジックインメモリアーキテクチャ / 電流源制御 / 多値集積回路 / 差動対回路 / ロジックインメモリVLSI / Ｘネット / 線形加算 |
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| Outline of Final Research Achievements |
A packet data transfer scheme (PDTS) is introduced to reduce configuration/control memory (CCM) size of a multiple-valued dynamic reconfigurable VLSI based on a logic-in-memory architecture. In the PDTS, the advantage is that remarkable reduction of the CCM size can be achieved in comparison with the conventional control scheme. Moreover, the PDTS contributes to fine-grain on/off control of the current sources in differential-pair circuits utilizing flag information which indicates the data is valid or invalid. Another type of a fine-grain reconfigurable VLSI is also proposed to enhance the hardware resource utilization. The basic cell consists of a multiple-valued multiplexer and a switch box connected with the adjacent cells. A latch can be implemented utilizing the multiplexer, so that the cell can be programmed as both logic and storage functions.
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