Memory device based on impurity nuclear spins in gate insulating layer of MOS device
| Project/Area Number |
26630167
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Institute of Physical and Chemical Research |
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Principal Investigator |
Ono Keiji 国立研究開発法人理化学研究所, 石橋極微デバイス工学研究室, 専任研究員 (00302802)
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| Project Period (FY) |
2014-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2016: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2015: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2014: ¥2,730,000 (Direct Cost: ¥2,100,000、Indirect Cost: ¥630,000)
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| Keywords | 電子スピン / 核スピン / 量子ドット / 半導体 / スピン |
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| Outline of Final Research Achievements |
In the silicon MOS transistor structure, localized levels are intentionally introduced into the gate insulating film by the introduction of impurities like donor and acceptor. The tunneling conduction via such localized state appeared as the gate leakage current. Focusing on the similarity between this leakage current and the transport of quantum dot device where an electric conduction occur via "artificially formed localized state", the applicant has examined the electrical control of the electron spin and the nuclear spin state of the localized level in the insulating film in the MOS structure based on the knowledge and experience concerning the electric conduction through the electric conductor, especially the electron spin / nuclear spin effect appearing therein. This study explore the possibility of a new memory device that use a nuclear spins as a memory element.
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Report
(4 results)
Research Products
(19 results)
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[Presentation] ON current boosting in Silicon-based Tunnel FETs Utilizing Isoelectronic Trap Technology2015
Author(s)
T. Mori, Y. Morita, S. Migita, K. Hukuda, Q. Mizubayashi, T. Yasuda, M. Masahoku, T. Matsukawa, H. Ota, S. Moriyama, K. Ono, S. Iizuka, T. Nakayama
Organizer
The 2015 International Workshop on “Dielectric Thin Films for Future Electron Devices (2015 IWDTF)
Place of Presentation
Miraikan（東京都・江東区）
Year and Date
2015-11-03
Related Report
Int'l Joint Research / Invited
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