Arbitrary data-width cache memory architecture in multi-FPGA systems

Research Project

Project/Area Number	26730026
Research Category	Grant-in-Aid for Young Scientists (B)
Allocation Type	Multi-year Fund
Research Field	Computer system
Research Institution	University of Tsukuba
Principal Investigator	Kanazawa Kenji 筑波大学, システム情報系, 助教 (40707874)
Project Period (FY)	2014-04-01 – 2017-03-31
Project Status	Completed (Fiscal Year 2016)
Budget Amount *help	¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000) Fiscal Year 2016: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000) Fiscal Year 2015: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000) Fiscal Year 2014: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Keywords	FPGA / キャッシュ / リコンフィギュラブルシステム / 可変キャッシュ / 充足可能性問題 / リコンフィギュラブルシステム
Outline of Final Research Achievements	We studied arbitrary data-width cache memory architecture in multi-FPGA systems which consist of multiple FPGAs and off-chip DRAMs. Using the number of FPGAs and topologies of the interconnect of the FPGAs as parameters, we evaluated its performance on several applications including the satisfiability (SAT), the maximum satisfiability (MaxSAT), the partial-MaxSAT, calculation of convex hulls and the quadratic assignment problems, and then made it clear which configuration achieved the maximum performance for each application.

Report

(4 results)