Arbitrary data-width cache memory architecture in multi-FPGA systems
| Project/Area Number |
26730026
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system
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| Research Institution | University of Tsukuba |
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Principal Investigator |
Kanazawa Kenji 筑波大学, システム情報系, 助教 (40707874)
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| Project Period (FY) |
2014-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
Fiscal Year 2016: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2015: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2014: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
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| Keywords | FPGA / キャッシュ / リコンフィギュラブルシス テム / 可変キャッシュ / 充足可能性問題 / リコンフィギュラブルシステム |
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| Outline of Final Research Achievements |
We studied arbitrary data-width cache memory architecture in multi-FPGA systems which consist of multiple FPGAs and off-chip DRAMs. Using the number of FPGAs and topologies of the interconnect of the FPGAs as parameters, we evaluated its performance on several applications including the satisfiability (SAT), the maximum satisfiability (MaxSAT), the partial-MaxSAT, calculation of convex hulls and the quadratic assignment problems, and then made it clear which configuration achieved the maximum performance for each application.
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Report
(4 results)
Research Products
(4 results)
