Design Technology Development for Acceleration and Low Power Consumption in Digital Integrated Circuit
| Project/Area Number |
26730029
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system
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| Research Institution | The University of Aizu |
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Principal Investigator |
Kohira Yukihide 会津大学, コンピュータ理工学部, 上級准教授 (00549298)
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| Project Period (FY) |
2014-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2016: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2015: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2014: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
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| Keywords | 集積回路設計自動化 / 低消費電力化 / 高速化 / 一般同期方式 / 多電源設計 / レイアウト設計 / 多電源集積回路設計 |
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| Outline of Final Research Achievements |
In this research, we developed a design automation system that realized both acceleration and low power consumption. The developed system combined multiple power supply voltages in which power consumption is reduced by assigning appropriate power supply voltage to each COMS gate, and general-synchronous framework in which the clock frequency is improved by utilizing the clock skew efficiently. In computational experiments, the circuits obtained by the developed system simultaneously realized higher circuit performance and lower power consumption than that in conventional clock synchronous framework.
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Report
(4 results)
Research Products
(6 results)
