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Design Technology Development for Acceleration and Low Power Consumption in Digital Integrated Circuit

Research Project

Project/Area Number 26730029
Research Category

Grant-in-Aid for Young Scientists (B)

Allocation TypeMulti-year Fund
Research Field Computer system
Research InstitutionThe University of Aizu

Principal Investigator

Kohira Yukihide  会津大学, コンピュータ理工学部, 上級准教授 (00549298)

Project Period (FY) 2014-04-01 – 2017-03-31
Project Status Completed (Fiscal Year 2016)
Budget Amount *help
¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2016: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2015: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2014: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Keywords集積回路設計自動化 / 低消費電力化 / 高速化 / 一般同期方式 / 多電源設計 / レイアウト設計 / 多電源集積回路設計
Outline of Final Research Achievements

In this research, we developed a design automation system that realized both acceleration and low power consumption. The developed system combined multiple power supply voltages in which power consumption is reduced by assigning appropriate power supply voltage to each COMS gate, and general-synchronous framework in which the clock frequency is improved by utilizing the clock skew efficiently. In computational experiments, the circuits obtained by the developed system simultaneously realized higher circuit performance and lower power consumption than that in conventional clock synchronous framework.

Report

(4 results)
  • 2016 Annual Research Report   Final Research Report ( PDF )
  • 2015 Research-status Report
  • 2014 Research-status Report
  • Research Products

    (6 results)

All 2017 2016 2015 2014

All Journal Article (2 results) (of which Peer Reviewed: 2 results,  Acknowledgement Compliant: 2 results) Presentation (4 results) (of which Int'l Joint Research: 1 results)

  • [Journal Article] Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework2016

    • Author(s)
      Junki KAWAGUCHI, Hayato MASHIKO, Yukihide KOHIRA
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E99.A Issue: 7 Pages: 1366-1373

    • DOI

      10.1587/transfun.E99.A.1366

    • NAID

      130005159600

    • ISSN
      0916-8508, 1745-1337
    • Related Report
      2016 Annual Research Report
    • Peer Reviewed / Acknowledgement Compliant
  • [Journal Article] 2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework2014

    • Author(s)
      Yukihide KOHIRA, Atsushi TAKAHASHI
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E97.A Issue: 12 Pages: 2459-2466

    • DOI

      10.1587/transfun.E97.A.2459

    • NAID

      130004706409

    • ISSN
      0916-8508, 1745-1337
    • Related Report
      2014 Research-status Report
    • Peer Reviewed / Acknowledgement Compliant
  • [Presentation] 歩留まり改善を考慮した電力削減のための製造後遅延調整手法2017

    • Author(s)
      増子駿,小平行秀
    • Organizer
      電子情報通信学会VLD研究会
    • Place of Presentation
      沖縄県青年会館(沖縄県那覇市)
    • Year and Date
      2017-03-01
    • Related Report
      2016 Annual Research Report
  • [Presentation] Yield and Power Improvement Method by Post-Silicon Delay Tuning and Technology Mapping2016

    • Author(s)
      Hayato MASHIKO, Yukihide KOHIRA
    • Organizer
      2016 IEEE Asia Pacific Conference on Circuits and Systems
    • Place of Presentation
      Ramada Plaza Jeju Hotel (Jeju, Korea)
    • Year and Date
      2016-10-27
    • Related Report
      2016 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Technology Mapping Method for Low Power Consumption and High Performance in General-Synchronous Framework2015

    • Author(s)
      Junki KAWAGUCHI, Yukihide KOHIRA
    • Organizer
      The 19th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2015)
    • Place of Presentation
      Evergreen Resort Hotel (Yilan, Taiwan)
    • Year and Date
      2015-03-25
    • Related Report
      2014 Research-status Report
  • [Presentation] 一般同期方式における低電力化と高速化を実現するためのテクノロジーマッピング手法2014

    • Author(s)
      川口純樹, 小平行秀
    • Organizer
      電子情報通信学会VLD研究会
    • Place of Presentation
      ビーコンプラザ (大分県別府市)
    • Year and Date
      2014-11-26
    • Related Report
      2014 Research-status Report

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Published: 2014-04-04   Modified: 2018-03-22  

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