| Project/Area Number |
26820121
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tohoku University |
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Principal Investigator |
Kuroda Rihito 東北大学, 工学(系)研究科(研究院), 准教授 (40581294)
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| Project Period (FY) |
2014-04-01 – 2016-03-31
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| Project Status |
Completed (Fiscal Year 2015)
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| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2015: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2014: ¥2,860,000 (Direct Cost: ¥2,200,000、Indirect Cost: ¥660,000)
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| Keywords | 電子デバイス・電子機器 / 電子デバイス・集積回路 / しきい値ばらつき / ランダム・テレグラフ・ノイズ / 原子レベル平坦化 / 電子デバイス・機器 / ランダムテレグラフノイズ |
|---|
| Outline of Final Research Achievements |
Atomically flattening technology of Si surface was introduced to a 0.22μm LSI manufacturing technology with shallow trench isolation process, and the atomic flatness of gate insulator/Si interface of MOS transistors was successfully obtained on the whole surface of 200mm diameter Si wafers. Based on the electrical characteristics measurement of over a million transistors, a reduction of threshold voltage variation as well as the one order of magnitude reduction of occurrence probability of random telegraph noise were confirmed and its reduction mechanism was clarified.
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