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Self-learnable Analog-Digital-Mixed VLSI Processors for Smart Human-Computer-Interaction

Research Project

Project/Area Number 26870227
Research Category

Grant-in-Aid for Young Scientists (B)

Allocation TypeMulti-year Fund
Research Field Human interface and interaction
Electron device/Electronic equipment
Research InstitutionNara Institute of Science and Technology (2017)
Japan Advanced Institute of Science and Technology (2014-2016)

Principal Investigator

ZHANG Renyuan  奈良先端科学技術大学院大学, 情報科学研究科, 助教 (00709131)

Project Period (FY) 2014-04-01 – 2018-03-31
Project Status Completed (Fiscal Year 2017)
Budget Amount *help
¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
Fiscal Year 2016: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2015: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2014: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
KeywordsAnalog-Digital-Hybrid / Approximate Computing / Analog Calculator / Multi-Valued-Logic / Approximate computing / Analog Calculation Unit / Image processing / Support Vector Machine / Analog-Digital-Mixed / Hybrid computing / Multi-Valued Logic / HCI / Neuron-MOS / FPGA / Multi-Valued Logics
Outline of Final Research Achievements

The analog-digital-hybrid computing processors have been developed for the human-computer-interaction (HCI) relevant applications. The approximate computing technologies were implemented in silicon to offer a different computing methodology from traditional binary processing on the basis of “deductive computation”. In this manner, the performances on computing speed and energy consumption were greatly improved. The ACU processor was successfully developed as the world-first programmable analog calculator for multi-operand calculation, which greatly speeds up the widely applied HCI technologies such as CNN.

Report

(5 results)
  • 2017 Annual Research Report   Final Research Report ( PDF )
  • 2016 Research-status Report
  • 2015 Research-status Report
  • 2014 Research-status Report
  • Research Products

    (12 results)

All 2018 2017 2016 2015 2014

All Journal Article (1 results) (of which Peer Reviewed: 1 results,  Open Access: 1 results,  Acknowledgement Compliant: 1 results) Presentation (11 results) (of which Int'l Joint Research: 7 results,  Invited: 1 results)

  • [Journal Article] Robust and Low-Power Digitally-Programmable-Delay-Element Designs Employing Neuron-MOS Mechanism2015

    • Author(s)
      R. Zhang, and M. Kaneko
    • Journal Title

      ACM Tran. Des. Autom. Electron. Syst. (TODAES)

      Volume: Vol. 20, No. 4 Issue: 4 Pages: 1-19

    • DOI

      10.1145/2740963

    • Related Report
      2015 Research-status Report 2014 Research-status Report
    • Peer Reviewed / Open Access / Acknowledgement Compliant
  • [Presentation] Analog Calculation Unit: A Solution of Approximate Computing2018

    • Author(s)
      Renyuan Zhang
    • Organizer
      International Workshop on Frontiers in Computing Systems and Wireless Communications
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] A Random Access Analog Memory with Master-Slave Structure for Implementing Hexadecimal Logic2017

    • Author(s)
      Renyuan Zhang
    • Organizer
      IEEE Int. Conf. System-on-Chip, (SOCC)
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A Feasibility Study of Programmable Analog Cal-culation Unit for Approximate Computing2017

    • Author(s)
      Renyuan Zhang
    • Organizer
      The Fifth International Symposium on Compu-ting and Networking, (CANDAR)
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A Feasibility Study of Master-Slave Flipflop Design for Hexadecimal Logic2016

    • Author(s)
      R. Zhang and M. Kaneko
    • Organizer
      IEEE Industrial Electronics and Applications Conference
    • Place of Presentation
      Kota Kinabalu, Malaysia
    • Year and Date
      2016-11-20
    • Related Report
      2016 Research-status Report
    • Int'l Joint Research
  • [Presentation] 16-Valued Logic FPGA Architecture Employing Analog Memory Circuit2016

    • Author(s)
      R. Zhang and M. Kaneko
    • Organizer
      IEEE Symposium of Circuits and Systems
    • Place of Presentation
      Montreal, Canada
    • Year and Date
      2016-05-22
    • Related Report
      2016 Research-status Report
    • Int'l Joint Research
  • [Presentation] A 16-Valued Logic FPGA Architecture Employing Analog Memory Circuit2016

    • Author(s)
      R. Zhang, and M. Kaneko
    • Organizer
      IEEE Int. Symp. Circ.s and Syst.s, (ISCAS)
    • Place of Presentation
      Montreal, Canada
    • Year and Date
      2016-05-22
    • Related Report
      2015 Research-status Report
    • Int'l Joint Research
  • [Presentation] A Feasibility Study of Quaternary FPGA Designs by Implementing Neuron-MOS Mechanism2015

    • Author(s)
      Renyuan Zhang, and Mineo Kaneko
    • Organizer
      IEEE International Symposium on Circuits and Sysstems 2015
    • Place of Presentation
      Lisbon, Portugal
    • Year and Date
      2015-05-24 – 2015-05-27
    • Related Report
      2014 Research-status Report
  • [Presentation] A Feasibility Study of Quaternary FPGA Designs by Implementing Neuron-MOS Mechanism2015

    • Author(s)
      R. Zhang, and M. Kaneko
    • Organizer
      IEEE Int. Symp. Circ.s and Syst.s, (ISCAS)
    • Place of Presentation
      Lisbon, Portugal
    • Year and Date
      2015-05-24
    • Related Report
      2015 Research-status Report
    • Int'l Joint Research
  • [Presentation] A Quaternary Master-Slave Flip-Flop with Multiple Functions for Multi-Valued Logics2015

    • Author(s)
      Renyuan Zhang, and Mineo Kaneko
    • Organizer
      The 19th Workshop on Synthesis and System Integration of Mixed Information Technologies
    • Place of Presentation
      Yilan, Taiwan
    • Year and Date
      2015-03-16 – 2015-03-17
    • Related Report
      2014 Research-status Report
  • [Presentation] A Temperature and Process Variation Insensitive PDE Circuit Employing Neuron-MOS2014

    • Author(s)
      Renyuan Zhang, and Mineo Kaneko
    • Organizer
      IEEE/ACM International Conference on Computer Aided Design, Workshop on VMC
    • Place of Presentation
      San Jose, USA
    • Year and Date
      2014-11-03 – 2014-11-06
    • Related Report
      2014 Research-status Report
  • [Presentation] A Feasibility Study on Robust Programmable Delay Element Design based on Neuron-MOS Mechanism2014

    • Author(s)
      Renyuan Zhang, and Mineo Kaneko
    • Organizer
      Great Lake Symposium on VLSI 2014
    • Place of Presentation
      Houston, USA
    • Year and Date
      2014-05-21 – 2014-05-23
    • Related Report
      2014 Research-status Report

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Published: 2014-04-04   Modified: 2019-03-29  

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