| Project/Area Number |
58850063
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| Research Category |
Grant-in-Aid for Developmental Scientific Research
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | University of Tsukuba |
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Principal Investigator |
ITANO Kozo 筑波大学, 電情, 講師 (20114035)
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| Project Period (FY) |
1983 – 1985
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| Project Status |
Completed (Fiscal Year 1985)
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| Budget Amount *help |
¥9,800,000 (Direct Cost: ¥9,800,000)
Fiscal Year 1985: ¥1,000,000 (Direct Cost: ¥1,000,000)
Fiscal Year 1984: ¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 1983: ¥5,300,000 (Direct Cost: ¥5,300,000)
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| Keywords | high-level Language / high-level language computer architecture / direct-execution computer / interactive programming / microprocessor / microprogramming / pipeline architecture / 性能評価 |
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| Research Abstract |
A Universal Direct-Execution Computer(UDEC) has been designed and built as an architecture executing a source program directly without compilation, for the basis of the realization of a highly interactive programming environment of procedure oriented languages. The UDEC consists of a language processor and an interactive processor. The language processor incorporates a pipeline architecture connecting the lexical processor, the syntax and semantics recognizer, and execution processor. To increase language independence, an interpretation grammar has been introduced and semantic actions are described being combied with the production rules of the language. The interpretation grammar is then transformed into a table driven control algorithm as far as possible in the lexical processor and the syntax and semantics recognizer, although the semantic actions are coded in microprogram due to its complexity. The interactive processor is implemented as a microcomputer with three high resolution display terminals to realize a highly interactive interface with users. To evaluate and improve the direct-execution algorithm and the architecture of the UDEC, the control algorithm for a PASCAL subset has been implemented. A register transfer level simulator and a profile analyzer were also implemented, and detail simulation was done analyzing the dynamic behavior of the language processor. The simulation has been done on VAXII/750 UNIX executing several sample programs. The simulation results showed that high speed hardware stack, hardware associative search mechanism, and address calculation mechanism are strongly effective as well as the functional module level pipeline architecture.
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