| Project/Area Number |
59850059
|
|---|
| Research Category |
Grant-in-Aid for Developmental Scientific Research
|
| Allocation Type | Single-year Grants |
|---|
| Research Field |
計算機工学
|
|---|
| Research Institution | Kyoto University |
|---|
Principal Investigator |
|
|---|
| Project Period (FY) |
1984 – 1985
|
| Project Status |
Completed (Fiscal Year 1985)
|
| Budget Amount *help |
¥7,800,000 (Direct Cost: ¥7,800,000)
Fiscal Year 1985: ¥3,400,000 (Direct Cost: ¥3,400,000)
Fiscal Year 1984: ¥4,400,000 (Direct Cost: ¥4,400,000)
|
|---|
| Keywords | High-Level Hardware Description / Logic Simulator / Logic Design Verification / Vector Processor / Hardware Design Language / Formal Verification / グラフィクス・ワークステーション |
|---|
| Research Abstract |
Hierarchical design method which repeats refinement of design from architectural level to gate level is suitable for designing of large scale logic circuits. In such a design methodology it is very important to verify each refinement step and to find out design error as early as possible. In order to support such verification step, we have researched on high-level hardware description languages which support design refinement step, high-speed logic simulation algorithms, and formal verification methods. Based on the results of these researches, we have also developed an interactive logic simulator-verifier. The major results of our researches are as follows.
1. High-Level Hardware Description: In order to support refinement of design, we have developed a new hardware design language HDL-R which supports multiple abstracted time and specification of correspondence in refinement of design. It is suitable for reliable design through architecture to register transfer level design.
2. High-Speed Logic Simulation Using a Vector Processor: We have developed new logic simulation algorithms named vector-parallel method and gate-grouping method. They are oriented to vector processors, and realized 7.7M gate evaluation/sec which is comparable to hardware simulation engines.
3. Formal Specification and Verification: We proposed a new model for parallel systems which treats time and cause-effect relations as partial ordering over events. This model enables us to give formal specification algebraically using abstract data types and to make formal verification.
4. Graphics Workstation: We have proposed and developed multicomputermultiscreen graphics as a workstation for the interactive logic simulatorverifier. It can realize any high resolution screen over technological limitation on resolutions of CRTs.
|
