| Project/Area Number | 60302049 |
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| Research Category |
Grant-in-Aid for Co-operative Research (A)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | HIROSHIMA UNIVERSITY |
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Principal Investigator |
KINOSHITA KOZO Faculty of Integrated Arts and Sciences, Hiroshima University, 総合科学部, 教授 (00028995)
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| Co-Investigator(Kenkyū-buntansha) |
KIKUNO Tohru Faculty of engineering Science, Osaka University, 基礎工学部, 助教授 (50093745)
MUKAIDONO Masao Faculty of Engineering, Meiji University, 工学部, 教授 (00061987)
TAKAMATSU Yuzo Faculty of Engineering, Ehime University, 工学部, 教授 (80039255)
OKAMOTO Takuji Faculty of Engineering, Okayama University, 工学部, 教授 (60032934)
TOHMA Yoshihiro Faculty of Engineering, Tokyo Institute of Technology, 工学部, 教授 (50016317)
古賀 義亮 防衛大学校, 教授
内藤 祥雄 長岡技術科学大学, 工学部, 助教授 (00115114)
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| Project Period (FY) |
1985 – 1987
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| Project Status |
Completed(Fiscal Year 1987)
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| Budget Amount *help |
¥5,900,000 (Direct Cost : ¥5,900,000)
Fiscal Year 1987 : ¥1,800,000 (Direct Cost : ¥1,800,000)
Fiscal Year 1986 : ¥1,800,000 (Direct Cost : ¥1,800,000)
Fiscal Year 1985 : ¥2,300,000 (Direct Cost : ¥2,300,000)
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| Keywords | Fault-Tolerant Computer / Fault-Tolerant System / Intelligent Systems / Fault-Tolerant Design / Testable design / Highly Reliable Design / Fault Detection and Diagnosis / 故障診断 / 設計検証 / フォールトトレランス / 高信頼化 / 知識工学 / ソフトウェアの高信頼化 / VLSI設計自動化 |
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| Research Abstract |
By the advent of VLSI techology, hardware cost is decreasing progressively. This fact enables to use an enormous amount of hardwares in computer systems. Therefore, fault-tolerant teques, which are mostly based on redundancy techniques, come to be more practical even for computers of commercial use. On the other hand, AI techniques aim at the realization of computer systems to be easily handled. This project, as an intersection of fault-tolerant and AI techniques, has been done concerning the following subjects. A) Cluster-based approach to fault-tolerant networks. B) Verification of system design including the time as a parameter. C) Intelligent robust data base. D) Testability design of ramdon logic control circuits. E) Concurrent testing of RAM. F) Concurrent and rule based test generation. G) Testable design of PLAs. H) Dependable design of microprocessor systems. I) Fuzzy computers and fault-tolerance. J) Self-checking circuits.
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