Investigation of Behaviours of Electrons in Ultra-thin Amorphous Silicon Layer and their Device Applications
| Project/Area Number |
60460061
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Applied materials
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
MATSUMURA Masakiyo Tokyo Institute of Technology, Professor, 工学部, 教授 (30110729)
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| Co-Investigator(Kenkyū-buntansha) |
KIMURA Ryuuhei Tokyo Institute of Technology, Assistant Researcher, 工学部, 助手 (80161587)
UCHIDA Yasutaka Tokyo Institute of Technology, Assistant Researcher, 工学部, 助手 (80134823)
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| Project Period (FY) |
1985 – 1986
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| Project Status |
Completed (Fiscal Year 1986)
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| Budget Amount *help |
¥7,700,000 (Direct Cost: ¥7,700,000)
Fiscal Year 1986: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 1985: ¥6,900,000 (Direct Cost: ¥6,900,000)
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| Keywords | Ultra-Thin Film / Amorphous-Silicon / Thin-Film Transistor / Thermal-Oxidation / Two-Step deposition / Self-Alignment / Plasma CVD / 半導体 / 絶縁体界面 |
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| Research Abstract |
This work has pointed out, for the first time, the technologcal importance of the ultra-thin active layer in amorphous-silicon transistors. This is because, by reducing the thickness, (1) cross section is reduced, (2) optical length is reduced, (3) recombination at the interface is enhanced and (4) optical band gap is enlarged. They result in the reduction of leakage current under illuminated conditions. Theoretical analysis has been carried out by taking the realistic logalized state density distribution into account. It was shown that when the thickness becomes less than 10nm, operating current of the transistor begins to increase.
By using conventional plasma CVD method, ultra-thin a-Si transistors have been fabricated and their performance has been evaluated. It became clear that theoretical results agree well with experimental results when the thickness is more than 20nm. However, the operating current is reduced rapidly by further thinning the active layer.
Origin of this discrepancy has been attributed to the non-uniform growth of the ultra-thin a-Si layer. To obtain uniform and ultra-thin a-Si layer, we have proposed a novel deposition method named as "two-step" deposition method, where dense a-Si nuclei is formed at the first stage of deposition and then the active a-Si layer of good electrical properties is deposited under the optimum deposition condition. By using this method, the 14nm thick transistor has been operated with large operating current and even 5nm thick transistor has been successfully operated.
Next, for the purpose of overcoming the problem caused by the back-side surface, we have developed a new surface treatment method named as "low-temperature thermal oxidation" method. By combining these results, novel self-alignment transistors have been developed. And we have also shown that the ultra-thin active layer is also effective to charge-coupled devices.
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Report
(1 results)
Research Products
(11 results)
