| Project/Area Number |
60460132
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
YONEDA Tomohiro (1986) Tokyo Institute of Technology , Research Associate, 工学部, 助手 (30182851)
南谷 崇 (1985) 東京工業大学, 工学部, 助教授
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| Co-Investigator(Kenkyū-buntansha) |
TOHMA Yoshihiro Tokyo Institute of Technology , Professor, 工学部, 教授 (50016317)
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| Project Period (FY) |
1985 – 1986
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| Project Status |
Completed (Fiscal Year 1986)
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| Budget Amount *help |
¥7,200,000 (Direct Cost: ¥7,200,000)
Fiscal Year 1986: ¥500,000 (Direct Cost: ¥500,000)
Fiscal Year 1985: ¥6,700,000 (Direct Cost: ¥6,700,000)
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| Keywords | Code disjoint / Concurrnt error detection / Error propagating interfaces / Error secure interfaces Fault secure / Microprocessor design / Self-testing / Strongly fault-secure systems / アーキテクチャ / VLSI / 耐故障 / 高信頼性 / フォールトトレラントシステム / セルフチェッキングプロセッサ / 超高信頼化システム / オンライン故障検出 |
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| Research Abstract |
A concept of the error secure and the error propagating interfaces of the subsystems in a digital system is introduced, and shown to be useful for practical design and verification for a strongly fault-secure system which is known to achieve the TSC goal. A sufficient condition is shown for subsystem interfaces to meet in order for it to be possible to construct a strongly fault-secure system with no checkers used to monitor the embedded interfaces. Based on the error secure/propagating concept, a design is presented for the strongly fault secure microprocessor which implements the instruction set of Intel's i8080 8-bit microprocessor. In the design, a complete set of building blocks is defined and all the partial interfaces are verified for the error secure/propagating property. Only four checkers are used at the embedded interfaces in the resulting strongly fault-secure processor.
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