Research on Design of VLSI Oriented Hardware Algorithms Using Redundant Representation
Grant-in-Aid for General Scientific Research (B)
|Allocation Type||Single-year Grants |
|Research Institution||Kyoto University |
YAJIMA Shuzo Faculty of Engineering,Kyoto University, 工学部, 教授 (20025901)
IWAMA Kazuo Institute of Computer Sciences,Kyoto Sangyo University, 計算機科学研究所, 助教授 (50131272)
OGINO Hiroyuki Faculty of Engineering,Kyoto University, 工学部, 教務職員 (40144323)
TAKAGI Naofumi Faculty of Engineering,Kyoto University, 工学部, 助手 (10171422)
YASUURA Hiroto Faculty of Engineering,Kyoto University, 工学部, 助教授 (80135540)
HIRAISHI Hiromi Faculty of Engineering,Kyoto University, 工学部, 講師 (40093299)
|Project Period (FY)
1985 – 1986
Completed (Fiscal Year 1986)
|Budget Amount *help
¥7,400,000 (Direct Cost: ¥7,400,000)
Fiscal Year 1986: ¥2,200,000 (Direct Cost: ¥2,200,000)
Fiscal Year 1985: ¥5,200,000 (Direct Cost: ¥5,200,000)
|Keywords||Hardware Algorithm / Redundant Representation / VLSI; Redundant Binary Representation / Arithmetic Operation / Residue Number Representation / Unification / 単一化操作 / ハードウェア設計言語|
In a design and development of complex VLSI, it is very important to design its hardware algorithm first so that we can realize high performance circuit. From this point of view, we have performed researches on design of VLSI oriented hardware algorithms using redundant representation. The main results are listed below:
1. Desing of Hardware Algorithms Using Redundant Representation
We proposed high speed hardware algorithms for elementary functions using a redundant binary representation. The redundant binary representation makes it possible to realize adder and subtracter of constant depth. By using these adder and subtracter, we have designed high speed circuits for various elementary functions.
2. Design of VLSI Oriented Hardware Algorithms by Means of Sophisticated Data Expressions and Data Structures
We have proposed an <OMICRON> (log n) depth n-bit binary division algorithm using residue number representation and designed a divider based on it. Furthermore, we proposed a high speed hardware algorithm for unification based on a new data structure named term graph.
3. Redundant Coding for High Speed Hardware Algorithms
We have proposed redundant coding methods which makes it possible to realize constant time hardware algorithms for operations on residue class and finite Abelian group.
4. Hardware Design Language Suitable for Step by Step Refinement
We have proposed a hardware design language which can describe hierarchical logic design of hardware with its hardware algorithms.
Report (1 results)
Research Products (18 results)