| Project/Area Number |
60850074
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| Research Category |
Grant-in-Aid for Developmental Scientific Research
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| Allocation Type | Single-year Grants |
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| Research Field |
計測・制御工学
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| Research Institution | TOHOKU UNIVERSITY |
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Principal Investigator |
HIGUCHI TATSUO TOHOKU UNIVERSITY, FACULTY OF ENGINEERING, 工学部, 教授 (20005317)
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| Co-Investigator(Kenkyū-buntansha) |
KANOMATA AKIO SENDAI RADTO TECHNICAL COLLEGE, 助教授 (20044654)
KAMEYAMA MICHITAKA TOHOKU UNIVERSITY, FACULTY OF ENGINEERING, 工学部, 助教授 (70124568)
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| Project Period (FY) |
1985 – 1986
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| Project Status |
Completed (Fiscal Year 1986)
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| Budget Amount *help |
¥3,700,000 (Direct Cost: ¥3,700,000)
Fiscal Year 1986: ¥900,000 (Direct Cost: ¥900,000)
Fiscal Year 1985: ¥2,800,000 (Direct Cost: ¥2,800,000)
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| Keywords | AI / Quaternary Integrated Circuit / Multiple Iron Implant / Pattern Matching Cell / 画像処理 / パターンマッチング / セル |
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| Research Abstract |
IT HAS BEEN WELL-KNOWN THAT THE PATTERN MATCHING IS A BASIC COMPONENT OF THE KNOWLEDGE INFORMATION PROCESSING SYSTEM INTERPRETERS. ON THE OTHER HAND, IT HAS BEEN LONG RECOGNIZED THAT THE USE OF MULTIPLE-VALUED LOGIC IN CONVENTIONAL DIGITAL SYSTEMS HAS POTENTIAL ADVANTAGES. ONE OF THE MOST IMPORTANT ADVANTAGES IS REDUCTION OF INTERCONNECTIONS ON A CHIP, SO THAT A HIGHLY COMPACT CHIP CAN BE REALIZED.
THIS PROJECT PRESENTS AN IMPLEMENTATION OF QUATERNARY INTEGRATED CIRCUITS FOR AI-ORIENTED PATTERN MATCHING CELLS AND THEIR APPLICATION TO IMAGE PROCESSING. A NEW PATTERN MATCHING CELL IS PROPOSED, SO THAT TWO DIFFERENT TEMPLATES CAN BE PROCESSED SIMULTANEOUSLY IN A PIPELINING MANNER. THE EASE OF THIS DOUBLE MATCHING PROCEDURE IS DUE TO THE FULL USE OF THE QUATERNARY INFORMATION IN THE MATCHED RESULT. THE BASIC BUILDING BLOCK OF THE CELL IS A QUATERNARY MULTIPLEXER WHICH IS ALSO CALLED A T-GATE. THE USE OF THE T-GATE ENABLES A STRUCTURED DESIGN OF ANY QUATERNARY LOGIC SYSTEM BECAUSE BOTH COMBINATIONAL AND SEQUENTIAL CIRCUITS CAN BE CONSTRUCTED USING ONLY T-GATES.
AN NMOS CHIP IS FABRICATED USING MULTIPLE IRON IMPLANT WHICH THE INVESTIGATOR HAS DEVELOPED. THE CHIP CONSISTS OF A 3-STAGE LINEAR ARRAY OF THE PATTERN MATCHING CELLS, DUAL T-GATES, A PATTERN MATCHING CELL, AND A 3-DIGIT DYNAMIC SHIFT REGISTER. THE CHIP SIZE IS 5 X 4 <mm^2> WITH A TOTAL OF 452 NMOS TRANSISTORS.
THE CHIP IS PROVED, BY MEASUREMENT, TO HAVE ALMOST THE DESIRED CHARACTERISTICS. ONE OF THE MOST IMPORTANT ADVANTAGES OF THE QUATERNARY IMAGE PROCESSING HARDWARE IS THAT THE NUMBER OF THE CELLS CAN BE REDUCED TO 50% OF THE CORRESPONDING BINARY IMPLEMENTATIONS BECAUSE OF THE DIRECT PROCESSING OF INPUT PIXELLS AND THE DOUBLE MATCHING PROCEDURE. SO, THE HIGHLY COMPACT PATTERN MATCHING CELL OBTAINED HERE IS VERY USEFUL AS AN AI-HARDWARE IN FUTURE.
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