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IMPLEMENTATION OF QUATERNARY INTEGRATED CIRCUITS FOR AI-ORIENTED PATTERN MATCHING CELLS AND THEIR APPLICATION

Research Project

Project/Area Number 60850074
Research Category

Grant-in-Aid for Developmental Scientific Research

Allocation TypeSingle-year Grants
Research Field 計測・制御工学
Research InstitutionTOHOKU UNIVERSITY

Principal Investigator

HIGUCHI TATSUO  TOHOKU UNIVERSITY, FACULTY OF ENGINEERING, 工学部, 教授 (20005317)

Co-Investigator(Kenkyū-buntansha) KANOMATA AKIO  SENDAI RADTO TECHNICAL COLLEGE, 助教授 (20044654)
KAMEYAMA MICHITAKA  TOHOKU UNIVERSITY, FACULTY OF ENGINEERING, 工学部, 助教授 (70124568)
Project Period (FY) 1985 – 1986
Project Status Completed (Fiscal Year 1986)
Budget Amount *help
¥3,700,000 (Direct Cost: ¥3,700,000)
Fiscal Year 1986: ¥900,000 (Direct Cost: ¥900,000)
Fiscal Year 1985: ¥2,800,000 (Direct Cost: ¥2,800,000)
KeywordsAI / Quaternary Integrated Circuit / Multiple Iron Implant / Pattern Matching Cell / 画像処理 / パターンマッチング / セル
Research Abstract

IT HAS BEEN WELL-KNOWN THAT THE PATTERN MATCHING IS A BASIC COMPONENT OF THE KNOWLEDGE INFORMATION PROCESSING SYSTEM INTERPRETERS. ON THE OTHER HAND, IT HAS BEEN LONG RECOGNIZED THAT THE USE OF MULTIPLE-VALUED LOGIC IN CONVENTIONAL DIGITAL SYSTEMS HAS POTENTIAL ADVANTAGES. ONE OF THE MOST IMPORTANT ADVANTAGES IS REDUCTION OF INTERCONNECTIONS ON A CHIP, SO THAT A HIGHLY COMPACT CHIP CAN BE REALIZED.
THIS PROJECT PRESENTS AN IMPLEMENTATION OF QUATERNARY INTEGRATED CIRCUITS FOR AI-ORIENTED PATTERN MATCHING CELLS AND THEIR APPLICATION TO IMAGE PROCESSING. A NEW PATTERN MATCHING CELL IS PROPOSED, SO THAT TWO DIFFERENT TEMPLATES CAN BE PROCESSED SIMULTANEOUSLY IN A PIPELINING MANNER. THE EASE OF THIS DOUBLE MATCHING PROCEDURE IS DUE TO THE FULL USE OF THE QUATERNARY INFORMATION IN THE MATCHED RESULT. THE BASIC BUILDING BLOCK OF THE CELL IS A QUATERNARY MULTIPLEXER WHICH IS ALSO CALLED A T-GATE. THE USE OF THE T-GATE ENABLES A STRUCTURED DESIGN OF ANY QUATERNARY LOGIC SYSTEM BECAUSE BOTH COMBINATIONAL AND SEQUENTIAL CIRCUITS CAN BE CONSTRUCTED USING ONLY T-GATES.
AN NMOS CHIP IS FABRICATED USING MULTIPLE IRON IMPLANT WHICH THE INVESTIGATOR HAS DEVELOPED. THE CHIP CONSISTS OF A 3-STAGE LINEAR ARRAY OF THE PATTERN MATCHING CELLS, DUAL T-GATES, A PATTERN MATCHING CELL, AND A 3-DIGIT DYNAMIC SHIFT REGISTER. THE CHIP SIZE IS 5 X 4 <mm^2> WITH A TOTAL OF 452 NMOS TRANSISTORS.
THE CHIP IS PROVED, BY MEASUREMENT, TO HAVE ALMOST THE DESIRED CHARACTERISTICS. ONE OF THE MOST IMPORTANT ADVANTAGES OF THE QUATERNARY IMAGE PROCESSING HARDWARE IS THAT THE NUMBER OF THE CELLS CAN BE REDUCED TO 50% OF THE CORRESPONDING BINARY IMPLEMENTATIONS BECAUSE OF THE DIRECT PROCESSING OF INPUT PIXELLS AND THE DOUBLE MATCHING PROCEDURE. SO, THE HIGHLY COMPACT PATTERN MATCHING CELL OBTAINED HERE IS VERY USEFUL AS AN AI-HARDWARE IN FUTURE.

Report

(2 results)
  • 1986 Final Research Report Summary
  • 1985 Annual Research Report
  • Research Products

    (14 results)

All Other

All Publications (14 results)

  • [Publications] 亀山,充隆: 1985 IEEE International Solid-State Circuits Conterence,Digest of Technical Papers. 86-87,315 (1985)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] 亀山,充隆: Poceedings of the 15th International Symposium on Multiple-Valued Logic. 226-232 (1985)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] 羽生貴弘: 電子通信学会論文誌. J69-D. 667-678 (1986)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] 羽生貴弘: 電子情報通信学会論文誌. J70-D. 493-496 (1987)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] 亀山充隆: IEEE Jounal of Solid-State Circuits. (1987)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] 羽生貴弘: Proceeding of the 17th International Symposium on Multiple-Valued Logic. (1987)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] MICHITAKA KAMEYAMA: "AN NMOS PIPELINED IMAGE PROCESSOR USING QUATERNARY LOGIC" 1985 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS. 86-87, 315 (1985)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] MICHITAKA KAMEYAMA: "IMPLEMENTATION OF QUATERNARY NMOS INTEGRATED CIRCUITS FOR PIPELINED IMAGE PROCESSING" PROCEEDINGS OF THE 15TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC. 226-232 (1985)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] TAKAHIRO HANYU: "DESIGN AND IMPLEMENTATION OF AN NMOS IMAGE PROCESSOR BASED ON QUATERNARY LOGIC" THE TRANSACTIONS OF THE INSTITUTE OF ELECTRONICS AND COMMUNICATION ENGINEERS OF JAPAN. J69-D. 667-678 (1986)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] TAKAHIRO HANYU: "DESIGN OF A QUATERNARY GATE ARRAY FOR HIGH-SPPED PATTERN MATCHING" THE TRANSACTIONS OF THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS OF JAPAN. J70-D. 493-496 (1987)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] MICHITAKA KAMEYAMA: "DESIGN AND IMPLEMENTATION OF QUATERNARY NMOS INTEGRATED CIRCUITS FOR PIPELINED IMAGE PROCESSING" IEEE JOURNAL OF SOLID-STATE CIRCUITS. (1987)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] TAKAHIRO HANYU: "QUATERNARY GATE ARRAY FOR PATTERN MATCHING AND ITS APPLICATION TO KNOWLEDGE INFORMATION PROCESSING SYSTEMS" PROCEEDINGS OF THE 17TH INTERNATIONAL SYMPOSIUM ON MULTIPLE VALUED LOGIC. (1987)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] Proc.of the Int.Symp.on Multiple Valued Logic. (1985)

    • Related Report
      1985 Annual Research Report
  • [Publications] 電子通信学会論文誌(D). (1986)

    • Related Report
      1985 Annual Research Report

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Published: 1987-03-31   Modified: 2016-04-21  

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