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Design and Implementation of an Automatic Vectorizing PASCAL Compiler

Research Project

Project/Area Number 60880007
Research Category

Grant-in-Aid for Developmental Scientific Research

Allocation TypeSingle-year Grants
Research Field Informatics
Research InstitutionKyoto University

Principal Investigator

TSUDA Takao  Dept. of Information Science, Faculty of Engineering, Kyoto University, 工学部, 教授 (60025905)

Co-Investigator(Kenkyū-buntansha) NAKAYA Itsuko  Dept. of Information Science, Faculty of Engineering, Kyoto University, 工学部情報工学科, 教務職員 (40115902)
KUNIEDA Yoshitoshi  Dept. of Information Science, Faculty of Engineering, Kyoto University, 工学部情報工学科, 助手 (90153311)
OKUBO Eiji  Dept. of Information Science, Faculty of Engineering, Kyoto University, 工学部情報工学科, 講師 (60127058)
Project Period (FY) 1985 – 1986
Project Status Completed (Fiscal Year 1986)
Budget Amount *help
¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 1986: ¥1,900,000 (Direct Cost: ¥1,900,000)
Fiscal Year 1985: ¥1,700,000 (Direct Cost: ¥1,700,000)
KeywordsVectorize / Automatic vectorization / PASCAL / Compiler / Vector machine / Nested loop / Control-dependence analysis / 一重化 / 自動ベクトル化コンパイラ / ベクトル化 / 並列化 / ループ選択 / ループ分割
Research Abstract

The compiler, which has resulted from this research project, is made of five phases. (1) Phase 1 : syntax and semantics analysis, (2) Phase 2 : pre-processing for vectorization, (3) Phase 3 : vectorizing and parallelizing, (4) Phase 4 : post-processing for vectorization, (5) Phase 5 : object-code generation. In phase 1, this compiler converts a given source program to specially designed intermediate codes. The source language is a subset of PASCAL 8000. In phase 2, the compiler optimizes the code and detects aliases. The optimizing techniques are chosen in such a way that they can : (A) increase vectorizable parts and (B) reduce costs of analyses. The phase 3 is made up from those modules given to : data-flow-analysis, control-flow analysis, dominator analysis, loop detection, control-dopendence analysis, data-dependence analysis, re-ordering of the intermediate codes, conversion of control structures, vectorization and parallelization. In phase 4, the compiler mainly optimizes scalar loops, and in phase 5, it generates machine codes. The target machine of this compiler is HITAC S-810, whose machine language allows us to express parallelism with ease. The size of the first version of this compiler is about 32,000 lines. The algorithm implemented in this compiler can vectorize the whole nested loops which may include If-then-else structures and/or exits from them, thus giving a breakthrough to the conventional vectorization technique.

Report

(2 results)
  • 1986 Final Research Report Summary
  • 1985 Annual Research Report
  • Research Products

    (8 results)

All Other

All Publications (8 results)

  • [Publications] T.Tsuda;Y.Kunieda: Proceedings of the IFIP 10th World Computer Congress. 785-790 (1986)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] 津田孝夫,国枝義敏,二宮正和,粟屋透: 情報処理学会論文誌. 26. 536-544 (1985)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] 津田孝夫,国枝義敏,二宮正和,粟屋透: 情報処理学会全国大会論文集 第29回. 【I】. 153-154 (1984)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] 津田孝夫,国枝義敏,二宮正和,粟屋透: 情報処理学会全国大会論文集 第29回. 【I】. 155-156 (1984)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] T. Tsuda, Y. Kunieda: "Mechanical Vectorization of Multiply Nested DO Loops by Vector Indirect Addressing" Proceedings of the IFIP 10th World Computer Congress. 785-790 (1986)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] T. Tsuda, Y. Kunieda, M. Ninomiya, T. Awaya: "Mechanical Vectorization of Multiply Nested DO Loops with Inter-Loop Data Dependences (in Japanese)" Transactions of Information Processing Society of Japan. 26. 536-544 (1985)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] T. Tsuda, Y. Kunieda, M. Ninomiya, T. Awaya: "Enhancement of Vectorization Ratio by Source Program Transformation. 1. Reduction of Multiple Loops to Single Loops (in Japanese)" Proceedings of 29th Nation Convention of IPSJ. I. 153-154 (1984)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1986 Final Research Report Summary
  • [Publications] T. Tsuda, Y. Kunieda, M. Ninomiya, T. Awaya: "Enhancement of Vectorization Ratio by Source Program Transformation. 2. Construction of a Vectorizing Preprocessor (in Japanese)" Proceedings of 29th Nation Convention of IPSJ. I. 155-156 (1984)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1986 Final Research Report Summary

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Published: 1987-03-31   Modified: 2016-04-21  

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