| Project/Area Number |
61460123
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
電子材料工学
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| Research Institution | Unicersity of Tokyo |
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Principal Investigator |
SUGANO Takuo Professor, University of Tokyo, 工学部, 教授 (50010707)
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| Co-Investigator(Kenkyū-buntansha) |
ARAI Fusako Assistant, University of tokyo (BABA,Hiroshi), 工学部, 助手 (10010927)
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| Project Period (FY) |
1986 – 1987
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| Project Status |
Completed (Fiscal Year 1987)
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| Budget Amount *help |
¥5,800,000 (Direct Cost: ¥5,800,000)
Fiscal Year 1987: ¥2,700,000 (Direct Cost: ¥2,700,000)
Fiscal Year 1986: ¥3,100,000 (Direct Cost: ¥3,100,000)
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| Keywords | Josephson junction / superconductine device / three terminal device / coplanar type device silicon device / シリコン・デバイス / 電界効果トランジスタ / ジョセフソン接合 / シリコン / デバイス |
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| Research Abstract |
Coplanar silicon-coupled Josephson juctions with recessed electrode structure were fabricated using a new planarization process. Niobium was used as superconducting electrode's material, and silicon, doped to degenerate in order to avoid freeze-out of carriers at liquid helium temperature, was used as the bridge connecting two superconducting electrodes. The electrode spacing was about 0.1 <micrn>. The fabrication procedure is as follows.
First, an n-type silicon wafer with (100) surface orientation was soped with boron to make p^+ thin layer on the surface. The boron doping was caried out by thermal diffusion using BN as dopant source at 1100゜c for 10 min. The junction depth and the surface concentration were estimated to be about 0.8 <micrn> and 4X10^<20> cm^-3, respectively.
The planarization process is as follows. (1)Polymethyl methacrylate (PMMA) was spun onto the doped silicon wafer. A fine line was delineated using electron beam, and a resist stencil was formed. (2)An aluminium li
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ne of about 0.1 <MU>m in width was formed by thermal evaporation of aluminium onto the stencil and subsequent lift-off of the stencil by soaking in acetone. (3)This line was used as a mask for the reactive ion etchin of silicon using CCl_2F_2 gas. The etching depth was 0.2 <micrn>. The aluminium mask was removed after etching silicon. (4) Niobium of 150 nm in thickness was deposited by electron beam evaporation. (5) By spinning polymer onto the wafer, the surface of the wafer was planarized. The thickness of the polymer was about 300 nm. (6) The polymer was etched using O_2 plasma, and the etching was stopped just after the niobium on top of the fine line appeared from the polymer layer. (7)The niobium on the line was etched using reactiv ion etching by CCl_2F_2 gas. (8)The remaining polymer layer was removed.
After obtaining the coplanar structure, niobium electrode was patterned using photolithography and reactive ion etching with CF_4 gas.
Electrical measurements were performed on the devices at liquid helium temperature and the operation of the devices was confirmed. The typical value of I_CR_N product was 10 <micrn>v. The critical current versus temperature was measured for silicon-coupled Josephson junction (B) and the coherence lenght of superconducting electrons in silicon was estimated to be 23 nm at 7.8 K.
Short channel MOS FETs with coplanar niobium electrodes were fabricated using the above described process and shallow doping technique. The channel length was 0.2 <micrn>m. The operation of The MOS FETs were confirmed at room temperature. Less
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