| Project/Area Number |
61460135
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
電子通信系統工学
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| Research Institution | Waseda University |
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Principal Investigator |
SHIRAI Katsuhiko Waseda University, School of Science and Engineering, 理工学部, 教授 (10063702)
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| Co-Investigator(Kenkyū-buntansha) |
MATSUYAMA Yasuo Ibaraki University, Faculty of Engineering, 工学部, 助教授 (60125804)
AKIZUKI Kageo Waseda University, School of Science and Engineering, 理工学部, 教授 (10063603)
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| Project Period (FY) |
1986 – 1987
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| Project Status |
Completed (Fiscal Year 1987)
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| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,900,000)
Fiscal Year 1987: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 1986: ¥2,800,000 (Direct Cost: ¥2,800,000)
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| Keywords | Speech recognition / Vector quantization / Architecture design / LSI CAD / Parallel processing / Pattern matcher / トランスピュータ / 話者識別 / データパス系合成 |
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| Research Abstract |
In order to realize a high performance speech recognition system, techniques to refer large amounts of knowledge base in real time should be developed. In the actual application areas of speech recognition, not only high recognition rate but low cost is strongly requested. Considering both requirements, this research aimed to study a parallel processing architecture suitable for the speech recognition and LSI architecture design system which particularly intended to produce digital signal processing LSIs. As for the parallel processing, a special experimental system was developed as a multiprocessor system composed of Transputers which are special microcomputers with communication links. Many kinds of pattern matching processes in speech recognition can be performed concurrently by exchanging intermediate matching. The system is tested by the task of parge vocabulary words recognition. It was verified that the parallel processing could effectively combine several kinds of paradigms developed for the word recognition.
The second objective of this research is to construct an architecture design system for LSIs. The input to this system is a specification description on the required function which is described by special high level specification language and the output is the hardware description at the register transfer level. LSIs can be produced from these decription by using the conventional CAD system. This study sdhowed a new possibility applying artificial intelligence technique to design problems.
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