Design of Highspeed Symbol Reader Integrated Circuit

Research Project

Project/Area Number	61550254
Research Category	Grant-in-Aid for General Scientific Research (C)
Allocation Type	Single-year Grants
Research Field	計算機工学
Research Institution	The University of Tokyo
Principal Investigator	WADA Eiiti Faculty of Engineering Professor, 工学部, 教授 (50010723)
Project Period (FY)	1986 – 1987
Project Status	Completed (Fiscal Year 1987)
Budget Amount *help	¥1,700,000 (Direct Cost: ¥1,700,000) Fiscal Year 1987: ¥400,000 (Direct Cost: ¥400,000) Fiscal Year 1986: ¥1,300,000 (Direct Cost: ¥1,300,000)
Keywords	Programming Language Processors / Name Table / Evaluation of Expressions / Combinators / Lisp / オブジェクトベクタ / LlSP / トライ型データ構造
Research Abstract	It had been often said that only 10 % of program code runs in 90 % of the total run time. In case of the pascal compiler, the symbol reader is such a heavt duty program. Symbol readers had to be tuned up intensively. Lately it became possible for the university laboratories to design special purpose integrated circuits. This project was to design a highspeed symbol reader circuit for program language processor. First, a symbol reader for Pascal compiler was designed. The first system implemented a scope controlled name table in the circuit because the name table search was considered as the most time consuming. Reserved words were registered in the circuit so that they should be discriminated from the identifiers and the corrosponding token code for each reserved word would be sent to the compiler. However, in the second system, besides the reserved words, special separaters such as semicolons and becomes symbols (:=) were to be token coded, numbers (integers and reals) were converted i … More nto binary forms, comments were skipped in the circuit. So, the design converged to the hardware counterpart of the normal symbol reader. This fact indicated that the symbol readers which treats non recursive part of the syntax was realy crealy cut from other part of the syntax analyzer. Then the possibilities were investigated whether the circuit was also applicable to Lisp interpreters because in case of Lisp, for each atomic symbols read in, the object vector search had to be conducted and it was also known time consuming. However, while designing the suitable archtecture for the Lisp interpreter circuit, it became apparent that it was rather hard to separate the token reader for atomic symbolswith the reason that modern Lisp treats strings freely and the strings and atomic symbols were often interchagable. Accordingly, it became necessary to include the larger part of the interpreter (probably excluding the garbage collector) in the chip. Therefore in the final year of the project, the research was centered around the expression evaluator in the chip where expressions were evaluated using the graph copy mechanism based on the combinator formalism. The simulation of the functional design indicates the chip will evaluate the expression 50 to 100 times faster than the ordinary interpreters. Less