| Project/Area Number |
61850061
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| Research Category |
Grant-in-Aid for Developmental Scientific Research
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | University of Tsukuba |
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Principal Investigator |
ITANO Kozo Institute of Information Sciences and Electronics, University of Tsukuba, 電子情報工学系, 助教授 (20114035)
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| Co-Investigator(Kenkyū-buntansha) |
ISHIHATA Kiyoshi Department of Information Science, Faculty of Science, University of Tokyo, 理学部・情報科学科, 助手 (70125988)
SIRAKAWA Tomonori Institute of Engineering Mechanics, University of Tsukuba, 構造工学系, 助教授 (20112021)
IDA Tetsuo Institute of Information Sciences and Electronics, University of Tsukuba, 電子情報工学系, 助教授 (70100047)
NAKATA Ikuo Institute of Information Sciences and Electronics, University of Tsukuba, 電子情報工学系, 教授 (70133022)
SASSA Masataka Institute of Information Sciences and Electronics, University of Tsukuba, 電子情報工学系, 助教授 (20016182)
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| Project Period (FY) |
1986 – 1988
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| Project Status |
Completed (Fiscal Year 1988)
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| Budget Amount *help |
¥20,000,000 (Direct Cost: ¥20,000,000)
Fiscal Year 1988: ¥5,000,000 (Direct Cost: ¥5,000,000)
Fiscal Year 1987: ¥7,200,000 (Direct Cost: ¥7,200,000)
Fiscal Year 1986: ¥7,800,000 (Direct Cost: ¥7,800,000)
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| Keywords | compiler / hardware compiler / hardware scanner / hardware parser / parallel sematic analysis / 手続き型言語 / ハードウエアコンパイラ / 言語処理系 / 字句解析プロセッサ / 構文解析プロセッサ / コード生成系 / パイプラインアーキテクチャ / ハードウエア記述言語 / レジスタ転送レベルシミュレーション / リングバス |
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| Research Abstract |
In order to execute a program at high speed, compilation is a very important process which transforms the source program into machine codes with optimization. However, the compilation takes a very large amount of the processing time of the computer in the program development system. This tendency is higher for the reseach and educational uses. This situation implies that we can increase the system performance by reducing compiling time, seperating it as a independent hardware unit from the host processor. Our reseach objective is to realize a hardware compile engine which can compile a source program very fast, e.g several ten times faster. Current complier implementation technology seems to be enough matured on software basis. Therefore, we analyzed these technology whether they are matched with hardware realization. On haredware dasis, detailed parallel processing is easily incorporated for speed-up. High speed table search can accelerate the processing speed. Some technolygy has been imported from the direct-execution computer of our preceding project. The design principles of the hardware complier is (1) language flexibility, (2) high-speed execution, and (3) modular design. Actually, the entire hardware is devided into four functional units: lexical unit, parsing unit, semantic unit, and code generator. These units are connnected in pipeline, and operated in parallel. The basic design of the lexical unit is inherited from that of the diret-execution computer, but simpified and a little bit slowed. The parser is designed on LR(1) basis which basically accepts the YACC parsing table. For the sematic analyzer, parallel analysis is to solve the buttle neck of the pipeline.
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