| Project/Area Number |
61850062
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| Research Category |
Grant-in-Aid for Developmental Scientific Research
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | Kyoto University |
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Principal Investigator |
YAJIMA Shuzo Professor, Faculty of Engineering, Kyoto University, 工学部, 教授 (20025901)
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| Co-Investigator(Kenkyū-buntansha) |
OGINO Hiroyuki Technical Official, Faculty of Engineering, Kyoto University, 工学部, 教務職員 (40144323)
ISHIURA Nagisa Research Associate, Faculty of Engineering, Kyoto University, 工学部, 助手 (60193265)
TAKAGI Naofumi Research Associate, Faculty of Engineering, Kyoto University, 工学部, 助手 (10171422)
YASUURA Hiroto Associate Professor, Faculty of Engineering, Kyoto Uniersity, 工学部, 助教授 (80135540)
HIRAISHI Hiromi Associate Professor, Faculty of Engineering, Kyoto Unversity, 工学部, 助教授 (40093299)
川久保 和雄 福山大学, 工学部, 助教授 (10186067)
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| Project Period (FY) |
1986 – 1987
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| Project Status |
Completed (Fiscal Year 1987)
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| Budget Amount *help |
¥7,300,000 (Direct Cost: ¥7,300,000)
Fiscal Year 1987: ¥3,000,000 (Direct Cost: ¥3,000,000)
Fiscal Year 1986: ¥4,300,000 (Direct Cost: ¥4,300,000)
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| Keywords | Logic Design Verification / Logic Simulation / Vector Processof / Temporal Logic / Specification Desctiption / Workstation / マルチスクリーン / 論理シミュレータ / 高水準ハードウェア記述 / 正則時相論理 / 代数的仕様記述 |
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| Research Abstract |
For a highly reliable design of large scale logic systems, it is essential to establish rigid methodologies and efficient support systems for design verificaion. From this point of view, we habe performed researches on development of high-speed logic simulators using a vector processor and logic design verification systems. Theis main results are listed below.
1. High-Speed Logic Simulators Using a Vector Processor We have developed simulation algorithms suitable for vector processing and implemented the simulators. For a zero-delay two-valued logic simulation, we have achived very high speed performance of 7.7x10^9 gate evaluation per second(combinational circuits) and 1.4x10^9 gate evaluation per second (sequential circuits). For a assignable-delay four-valued logic simulation,3.4x10^5 event per second have been achieved.
2. Logic Design Verification Systems
We have deceloped algorithms for decision problems of satisfiability and model checking of Regular Temporal Logic(RTL) which is expressively equivalent to the regular set. Based on these results, we have established design verification methods using the RTL. We have alse developed a timing verification method using #-expression, which is an extension of the regular expression.
3. Workstation for Logic Design
In order to display a large amount of information precisely and quikly, we have developed a workstation based on a multi-computer multi-screen method, which enables high-resolution display beyond the limit of a single screen and parallel high-speed drawign.
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