| Project/Area Number |
62460126
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | Kyoto University |
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Principal Investigator |
HAGIWARA Hiroshi Kyoto Univ.,Faculty of Eng.,Professor, 工学部, 教授 (00025818)
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| Co-Investigator(Kenkyū-buntansha) |
INOUE Tomoko Kyoto Univ.,Faculty of Eng.,Teaching Staff, 工学部, 教務職員 (40109145)
NIIMI Haruo Kyoto Univ.,Faculty of Eng.,Instructor, 工学部, 助手 (40144331)
SHIBAYAMA Kiyoshi Kyoto Univ.,Faculty of Eng.,Associate Professor, 工学部, 助教授 (70127091)
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| Project Period (FY) |
1987 – 1988
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| Project Status |
Completed (Fiscal Year 1988)
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| Budget Amount *help |
¥7,100,000 (Direct Cost: ¥7,100,000)
Fiscal Year 1988: ¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 1987: ¥3,600,000 (Direct Cost: ¥3,600,000)
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| Keywords | Parallel Machine / Parallel Processing / Logic Programming Language / Reduction Machine / グラフ・リダクション / 並列計算機 |
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| Research Abstract |
In this project, we developed the architecture of a multiprocessor system oriented to the logic programming language, called KPR, which can execute a program written in some paralled logic programming languages. The KPR system is controlled on the basis of a new computation model named "Parallel Reduction (PR-) model", which regards execution of a logic program as a combined process of searching assertions and traversing the corresponding AND/OR inference tree. On this PR-model, a logical process is allocated to a node of a process graph that is dynamically produced at execution time. And, the resultant reduction (folding / unfolding) of this AND/OR process graph is executed in parallel. This execution model was implemented by three kinds of porcesses as follows: (i) "Or-process" for implementing OR-parallelism of a logic program; (ii) "Stream-process" for realizing the AND-parallelsim by a stream-pipeline processing method; (iii) "Database-process"for managing an assertion database.
KPR is a heterogeneous-function distributed-processing system, where each process is executed on the specilized processor. The inter-processor network of KPR is realized by a tree-structured topology, each leaf node of which represents a processor element. The processor element is a tightly-coupled processor pair, called ORP (Or Reduction Processor) and ARP (And Reduction Processor). An intermediate network node is called NNC (Network Node Unit) and is provided with a bus-switching mechanism, status flag registers and a shared memory for storing global environment data. Some DBP's (DataBase Processors) will be attached to some of NNU's and the SVP (Supervisory Processor) will be attached to the root NNU.
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