| Project/Area Number |
62460127
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | Kyoto University |
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Principal Investigator |
TAMARU Keikichi Kyoto University, Faculty of Engineering, Professor, 工学部, 教授 (10127102)
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| Co-Investigator(Kenkyū-buntansha) |
ONODERA Hidetoshi Kyoto University, Faculty of Engineering, Instructor, 工学部, 助手 (80160927)
YASUURA Hiroto Kyoto University, Faculty of Engineering, Associate Proffesor, 工学部, 助教授 (80135540)
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| Project Period (FY) |
1987 – 1988
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| Project Status |
Completed (Fiscal Year 1988)
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| Budget Amount *help |
¥7,800,000 (Direct Cost: ¥7,800,000)
Fiscal Year 1988: ¥1,700,000 (Direct Cost: ¥1,700,000)
Fiscal Year 1987: ¥6,100,000 (Direct Cost: ¥6,100,000)
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| Keywords | Analog LSI / CAD System / Hierarchical Design / Symbolic Layout / Layout Editor / Methodology of Block Placement / Compaction / オペアンプの自動設計 / アナログ回路 / LSI / レイアウト / 回路解析 / 回路記述 / 自動設計 / デバイスシミュレータ |
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| Research Abstract |
With rapid progress in integrated circuit technologies, there is a growing demand for analog LSIs and mixed analog/digital LSIs. Existing CAD systems for LSI, however, mainly put their target on handle digital circuits. Few system can treats analog circuits, which makes the design cost of full custom analog circuits prohibitively high. Therefore, it is strongly required to establish the design methodology and CAD tool for analog circuits.
In this research project, we have investigated a CAD system for analog LSIs which has been constructed on the same framework as CAD systems for digital LSIs. Special interests have been put on the following points: how to introduce the concept of hierarchical design, how to manage the correspondence between circuit and layout, how to automate the optimization of various design parameters, and how to describe the design data for analog circuits. Brief descriptions of the obtained results are shown below.
1. Studies on an automatic synthesis system for analog circuits: A method has been proposed that utilizes a non-linear optimization technique for the determination of design parameters in analog circuits. This method is applied to an automatic design system for operational amplifiers which generates layout of an optimally designed circuit from its performance specifications.
2. Development of a hierarchical symbolic layout design system: A new layout design methodology using data description with correspondence between circuit and layout has been proposed. Based on the methodology, we have developed a symbolic layout design system which adopts newly developed hierarchical compaction method.
3. Studies on design language for analog circuits: To establish a design language for mixed analog/digital LSI, we participate an activity of standardization of LSI design language for JIS. By the above research activities, we obtained fundamental techniques for analog LSI CAD systems.
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