Study of a Reconfigurable Parallel Processor
| Project/Area Number |
62460129
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | Kyushu University |
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Principal Investigator |
TOMITA Shinji Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, 大学院総合理工学研究科, 教授 (40026323)
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| Co-Investigator(Kenkyū-buntansha) |
YOSHIDA Norihiko Faculty of Engineering, Kyushu University, 工学部, 助手 (00182775)
TANIGUCHI Rin-ichiro Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, 大学院総合理工学研究科, 助手 (20136550)
MURAKAMI Kazuaki Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, 大学院総合理工学研究科, 助手 (10200263)
FUKUDA Akira Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, 大学院総合理工学研究科, 助手 (80165282)
SUEYOSHI Toshinori Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, 大学院総合理工学研究科, 助教授 (00117136)
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| Project Period (FY) |
1987 – 1988
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| Project Status |
Completed (Fiscal Year 1988)
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| Budget Amount *help |
¥5,800,000 (Direct Cost: ¥5,800,000)
Fiscal Year 1988: ¥3,000,000 (Direct Cost: ¥3,000,000)
Fiscal Year 1987: ¥2,800,000 (Direct Cost: ¥2,800,000)
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| Keywords | Reconfigurability / Parallel processor / Interconnection network / Crossbar network / Parallel operating system / Task / Thread / 負荷分散方式 / パイプライン制御 / キャッシュコヒーレンス制御 / シミュレーション |
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| Research Abstract |
Main results in the project are as follows.
1.Studies on reconfigurableinterconnection networks. A crossbar network is chosen to attain arbitrary interconnection topologies. The network allows users to match a interconnection topology to a given algorithm. The modular 128X128 crossbar network is implemented by arranging 256 identical 8X8 crossbar LSI-modules in a 16X16 matrix form. A method where the network has switching patterns is proposed to prevent any contention from occurring at run time. By employing the method, high-speedinter-processor communication can be attained.
2.Development of processing elements. Reconfigurable memory architecture is implemented. The architecture allows the system to be reconfigured as a loosely coupled multiprocessor or a tightly coupled multiprocessor.
3.Development of a reconfigurable parallel processor. Message transmission between processors is pipelined to attain high-speed inter-processor communication. A reconfigurable parallel processor which employs the above architecturesis developed.
4. Studies on dynamic load balancing scheme. Task/thread-model is chosen as a good parallel processing model in a tightly coupled multiprocessor. A load balancing scheme where processor assign a task is proposed. By using the scheme, loads in the system can be distributed between processors, and overhead during context switching can be reduced. A high-level programming language which allows users to describe parallel processing models effectively and its language processor are developed.
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Report
(3 results)
Research Products
(19 results)
