Implementation and control of pipelineable fast IIR adaptive filters
| Project/Area Number |
62550241
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
電子通信系統工学
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| Research Institution | Kanazawa University |
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Principal Investigator |
TSUYOSHI Takebe Faculty of Technology, Kanazawa University, Professor, 工学部, 教授 (20019699)
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| Project Period (FY) |
1987 – 1988
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| Project Status |
Completed (Fiscal Year 1988)
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| Budget Amount *help |
¥1,300,000 (Direct Cost: ¥1,300,000)
Fiscal Year 1988: ¥400,000 (Direct Cost: ¥400,000)
Fiscal Year 1987: ¥900,000 (Direct Cost: ¥900,000)
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| Keywords | Adaptive filter / Echo canceller / All-pass network / Normalized LMS algorithm / Multi-signal processor implementation / シグナルプロセッサ応用 / マルチシグナルプロセッサ構成 / 直交関数系実現回路 / システム同定 / 有色信号 / 相関除去法 / ARモデル / 極配置法 / 状態変数形回路 / IIRフィルタ / 除算の高速化 |
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| Research Abstract |
This paper studies design and implementation of a new IIR adaptive filter. The filter has a structure like a transversal filter replaced their delay elements by second order all-pass sections. Any two of their tap responses are orthogonal. System identification is studied. Summary of the results are as follows:
1) The poles of all-pass networks are allotted on the circle in the z-plane, which pole spacing is proportional to the group delay of the object system. The learning characteristics are superior to that ot the frequency sampling adaptive filter. 2) In signal processor implementation of all-pass sections, state variable type has least operation steps. 3) For processing of colored signal, correlation removing algorthm is very effective, but variable step size algorithm is not. 4) Multiprocessor implementation is considered. An external RAM is shared with multiprocessors. All-pass part are pipe-linedly operated and weighting coefficients are adjusted with parallel processing.
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Report
(3 results)
Research Products
(12 results)
