| Project/Area Number |
62550271
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | Osaka Electro-Communication University, Faculty of Engineering |
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Principal Investigator |
ASANO Tetsuo Osaka Electro-Communication University, Faculty of Engineering, 工学部, 教授 (90113133)
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| Project Period (FY) |
1987 – 1988
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| Project Status |
Completed (Fiscal Year 1988)
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| Budget Amount *help |
¥2,000,000 (Direct Cost: ¥2,000,000)
Fiscal Year 1988: ¥500,000 (Direct Cost: ¥500,000)
Fiscal Year 1987: ¥1,500,000 (Direct Cost: ¥1,500,000)
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| Keywords | computational geometry / VLSI layout design / algorithm design / routing problem / clustering / VLSIレイアウト設計 / データ構造 / VLSI / レイアウト設計 / 配置配線設計 |
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| Research Abstract |
In this research we have applied algorithms and data structures developed in computational geometry to VLSI layout design, such as Bipolar LSI routing problem, module placement problem, and automatic compaction problem. We have developed an efficient algorithm for the first problem which runs in O(n log n) time while the traditional one requires O(n^2) time. For the second problem we first mapped modules onto points in the plane so that the distance is anti-proportional to the connectivity and then applied an algorithm for partitioning a point set into two under some geometric condition. We succeeded in improving the partition algorithm from O(n^2log^2n) time to O(n log n) time. Lastly we have developed a symbolic layout system with automatic compaction and very useful layout editor. One characteristic of the editor we can move a module together with their associated nets. The system is realized using data structures such as segment tree and binary search tree.
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