Development of a High-Performance Workstation with a Very-Long-Instruction-Word (VLIW) Processor
Grant-in-Aid for Developmental Scientific Research
|Allocation Type||Single-year Grants|
|Research Institution||Kyushu University|
TOMITA Shinji(1988) Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, 大学院総合理工学研究科, 教授 (40026323)
富田 真治(1987) 九州大学, 教授
YOSHIDA Norihiko Faculty of Engineering, Kyushu University, 工学部, 助手 (00182775)
TANIGUCHI Rin-ichiro Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, 大学院総合理工学研究科, 助手 (20136550)
MURAKAMI Kazuaki Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, 大学院総合理工学研究科, 助手 (10200263)
FUKUDA Akira Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, 大学院総合理工学研究科, 助手 (80165282)
SUEYOSHI Toshinori Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, 大学院総合理工学研究科, 助教授 (00117136)
|Project Period (FY)
1987 – 1988
Completed(Fiscal Year 1988)
|Budget Amount *help
¥23,200,000 (Direct Cost : ¥23,200,000)
Fiscal Year 1988 : ¥16,400,000 (Direct Cost : ¥16,400,000)
Fiscal Year 1987 : ¥6,800,000 (Direct Cost : ¥6,800,000)
|Keywords||Low-level parallel processing / VLIW(Very Long Instruction Word) architecture / Pipeline architecture / SIMP(Single Instruction stream / Multiple instruction Pipelining) architecture / Code scheduling / 動的コード・スケジューリング / 静的コード・スケジューリング / 最適化コンパイラ|
Main results of the project are summarized below.
1. Evaluation of the QA-series and Redesign of VLIW Architecture:
VLIW (Very Long Instruction Word) processors, such as the QA-series, can exploit low-level parallelism in the process of instruction execution. However, they have a serious drawback; i.e., it is difficult for VLIW architectures to keep program compatibility, because their architectures are exposed to compilers. As a result of the evalution, we have introduced a novel processor architecture, SIMP (Single Instruction stream/Multiple instruction Pipelining), as a deviation of VLIW. Given that P instruction pipelines are provided, SIMP porcessors ideally reduce the average number of cycles per instruction to 1/p by fetching P instructions per cycle. they can preserve program compatibility at the same time.
2. Development of the SIMP Processor Prototype:
As the first implementation of SIMP, we have developed the SIMP processor prototype. Degree of performance enhancement achieved by SIMP depends on; i) how to supply multiple instructions continuously and simultaneously, and ii) how to resolve data and control dependencies effectively. We have devised the algorithms for dependency resolution and instruction fetch. The dependency resolution algorithm permits out-of-order execution of sequential instruction stream with dynamic code scheduling.
3. Studies on Static code Scheduling:
Though the prototype employs dynamic code scheduling, it appreciates the advantage of static code scheduling. Static and dynamic code scheduling methods differ in their domain; i.e., static code scheduling is done with a broad overview of program codes, but dynamic code scheduling is done with a peephole. However, these code scheduling methods are not mutually exclusive. We have studied the adaptability of static code scheduling such as trace scheduling, software pipelining, polycyclic scheduling, and so on.
Research Products (11results)