| Project/Area Number |
62850069
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| Research Category |
Grant-in-Aid for Developmental Scientific Research
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| Allocation Type | Single-year Grants |
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| Research Field |
電子機器工学
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| Research Institution | Department of Electrical Engineering, Kyushu University |
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Principal Investigator |
MATSUYAMA Kimihide (1988-1989) Dep. of Electrical Engng., Kyushu Univ., Associate Prof., 工学部, 助教授 (80165919)
小西 進 (1987) 九州大学, 工学部, 教授
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| Co-Investigator(Kenkyū-buntansha) |
ASADA Hironori Dep. of Electrical Engng., Kyushu Univ., Assistant, 工学部, 助手 (70201887)
TOYOFUKU Shigeru Dep. of Electrical Engng., Kyushu Univ., Assistant, 工学部, 助手 (00037780)
HAYASHI Nobuo Dep. of Computer Science, Univ. of Electo-Commun., Prof., 電気通信学部, 教授 (90011585)
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| Project Period (FY) |
1987 – 1989
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| Project Status |
Completed (Fiscal Year 1989)
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| Budget Amount *help |
¥12,500,000 (Direct Cost: ¥12,500,000)
Fiscal Year 1989: ¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 1988: ¥3,400,000 (Direct Cost: ¥3,400,000)
Fiscal Year 1987: ¥5,500,000 (Direct Cost: ¥5,500,000)
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| Keywords | Magnetic Memory / Vertical Bloch Line / Magnetic Wall / Bubble Domain |
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| Research Abstract |
In order to put a nobel solid state magnetic memory (Bloch line memory) to practical use, the following memory functions were confirmed in a test chip processed on a LPE garnet film for 10 Mbit/cm^2 Bloch line memory (nominal stripe width is 5 um). 1. VBL storage area of 1 mm^2 was constructed by parallel grooved patterns formed by the wet etching method using heated phosphoric acid. 2. A computer controlled chip tester was fabricated, and the simultaneous read and write operations for multiple stripe domains was confirmed by the chip tester. 3. Bit stabilization effect due to the stress induced anisotropy caused by periodically patterned Cr film was studied numerically. Bit propagation of VBLs was realized in a test chip, which was fabricated according to the design criteria obtained from the numerical results. 4. A new architecture of major line bubble propagation path having large misalignment tolerance was processed. A read-write gate with the bubble propagation path was processed
… More
on a test chip. Sequential gate operations, that is, conversion of bit informations from VBLs to bubbles, bubble propagation, bubble stretching, were confirmed on the chip.
A read-write gate having reasonable operation margin was processed on a LPE garnet film for 40 Mbit/cm^2 Bloch line memory (nominal stripe width is 2 um) as a next step to increase the bit density. The temporal and spatial variations of the detailed micromagnetic structures during the wall merging process was studied numerically. It was found that the read operation error was caused by the dynamic wall structure change (nucleation of the horizontal Bloch line), and the operation condition to suppress it was clarified. Furthermore, An accurate mathematical formula for the effective wall-demagnetizing pressure was derived. The simulated result using the formula agreed well with the theory in the case of material with small characteristics factor (q=2.8), which would be used for Bloch line memory of more than 100 Mbit/cm^2. Less
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