| Budget Amount *help |
¥1,800,000 (Direct Cost: ¥1,800,000)
Fiscal Year 1989: ¥400,000 (Direct Cost: ¥400,000)
Fiscal Year 1988: ¥1,400,000 (Direct Cost: ¥1,400,000)
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| Research Abstract |
An arbitrary logic function can be realized by an AND-OR two-level circuit. In integrated circuits, two-level circuits are often realized as programmable logic arrays(PLA's). Because PLAs have regular structure, they are easy to design, easy to modify, and easy to test. Thus, recent VLSIs(very large scale integrations) use large PLAs in their control parts. However, the larger PLAs, the more sparse the connections in the arrays: i.e., large PLAs tend to waste silicon chip area.
One method to solve this problem is decomposition of PLAs, i.e., to realize given functions by using several smaller PLAs. Decomposition of PLAs can be classified into two types: serial decomposition and parallel decomposition. In the first type of the decomposition, in a serial decomposition, the input variables are partitioned into two groups, and the first PLA realizes intermediate functions and the second PLA realizes desired function. In the second type of the decomposition, in a parallel decomposition, the output functions are partitioned into two groups, and each PLA realizes each group independently. Because both types of decompositions can make total size of PLAs smaller than original ones, they are often used in modern micro processors.
In this research, we considered the serial and parallel decompositions of PLA's. Serial decompositions are effective when the total size of the decomposed PLA's is smaller than original one. Experimental results show that the serial decomposition reduce the total PLA size by 10 to 30 percents. As for parallel decomposition, the optimum decomposition is one with minimum delay, where we assume that the delay of the PLA is proportional to the number of product terms. We developed PDEC, an interactive tool to find a near optimum decomposition. We decomposed many arithmetic and control PLAs into two by using PDEC. We obtained PLAs with, on the average, 35% smaller delay and 6% less total array area in the case of control circuits.
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