| Project/Area Number |
63550297
|
|---|
| Research Category |
Grant-in-Aid for General Scientific Research (C)
|
| Allocation Type | Single-year Grants |
|---|
| Research Field |
計測・制御工学
|
|---|
| Research Institution | Tohoku University |
|---|
Principal Investigator |
KAMEYAMA Michitaka Tohoku University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (70124568)
|
|---|
| Project Period (FY) |
1988 – 1989
|
| Project Status |
Completed (Fiscal Year 1989)
|
| Budget Amount *help |
¥2,200,000 (Direct Cost: ¥2,200,000)
Fiscal Year 1989: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 1988: ¥1,100,000 (Direct Cost: ¥1,100,000)
|
|---|
| Keywords | VLSI processor / Robot electronics / Minimum delay time / Parallel processing / Coordinate transformation processor / Image recognition processor / Obstacle avoidance processor / Neural network / VISLプロセッサ / 画像確認プロセッサ / 障害物回避プロセッサ / VLSプロセッサ / データフローグラフ |
|---|
| Research Abstract |
In robot applications, it is necessary to respond immediately to the change of environment and to move according to the recognized results. A series of chains consisting of many kinds of processing is required between the environment recognition and the movement. In this case, it is necessary to minimize the absolute delay time in each processing module, so that the reduction of latency is very important in the design of VLSI processors for robotics. This research is dedicated for the above purpose, and the main results obtained are summarized as follows:
1.Effective Hardware Algorithm To minimize the absolute delay time an algorithm with less computational complexity is desirable. A typical example is the coordinate transformation processor that has been implemented with CMOS LSI. Two-dimensional coordinate rotation is effectively used as a basic operation, which makes the processing speed about 20 times faster than the conventional approach.
2.Highly Parallel architecture The use of parallelism is another effective approach to reduce the delay time. In the proposed architecture, the parallel processing elements oT subprocessors are connected through an interconnection network so that each data output is transferred immediately with minimum latency. The applications are also considered such as a matrix operation processor for digital servoing, an inverse dynamics processor, an image recognition processor based on chain-code matching and an obstacle avoidance processor.
3.Neural Network for Optimum Solution Discrete-time neural network for highly parallel hardware is proposed. The function of each cell is a multiply-add operation, so that optimum solutions are always obtained for the optimization problems such as the minimization of an evaluation function.
|
