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Data-Driven Ultra-Parallel Processing Scheme Based on "Flow-Thru Processing" Concept

Research Project

Project/Area Number 63850067
Research Category

Grant-in-Aid for Developmental Scientific Research (B).

Allocation TypeSingle-year Grants
Research Field 計算機工学
Research InstitutionOsaka University

Principal Investigator

TERADA Hiroaki  Osaka University, Faculty of Engineering, Professor, 工学部, 教授 (80028985)

Co-Investigator(Kenkyū-buntansha) NISHIKAWA Hiroaki  Osaka University, Faculty of Engineering, Research Associate, 工学部, 助手 (60180593)
SASAO Tsutomu  Kyushu Institute of Technology, Faculty of Computer Science & System Engineering, 情報工学部, 助教授 (20112013)
Project Period (FY) 1988 – 1990
Project Status Completed (Fiscal Year 1990)
Budget Amount *help
¥7,400,000 (Direct Cost: ¥7,400,000)
Fiscal Year 1990: ¥1,800,000 (Direct Cost: ¥1,800,000)
Fiscal Year 1989: ¥1,800,000 (Direct Cost: ¥1,800,000)
Fiscal Year 1988: ¥3,800,000 (Direct Cost: ¥3,800,000)
KeywordsUltra Parallel Algorithm / VLSI / Ultra Parallel Processing Scheme / Data-driven / Diagrammatical Language / Flow-thru Processing / Programmable Logic Array / Multiple Valued Logic / データ駆動
Research Abstract

This research was initiated to realize the ultra parallel processing scheme on a VLSI chip by introducing the "flow-thru processing" concept. In order to establish a basis for highly parallel algorithms, we have undertaken such examples as the prime number generation (Sieve of Eratosthenes) in which high parallelisms existent in the target problem must execute without any side effects. We have shown that the elastic pipeline based upon the "flow-thru processing" concept is effective in exploiting such parallelisms (reference no. 1). Next, a single board data-driven processor system also based upon the "flow-thru processing" concept was realized and has served as a powerful experimental system. Using the system's monitoring facilities, we have confirmed the targeted performance of 20 MOPS (reference no. 3). Performance evaluations of 40 MFLOPS were exhibited for the system's ALU, the floating point processor (reference no. 4). Evaluations also confirmed 50 mega associations per second f … More or the firing control function (reference no. 5). Encouraged from these results, a prototype of the one chip data-driven processor was fabricated as an evaluation chip which yielded performance of 50 MFLOPS (reference no. 6).
Focusing upon the field programmability of programmable logic arrays, we have also began preliminary examination on variable structure elastic pipelines in order to realize a processor with more flexible capabilities.
When interconnected, such a powerful single processor can also serve as processing elements in large scale multiprocessor system which promises to achieve breakthroughs in performance thus far unsuccessful with conventional processors. An antonomous distributed parallel associative processor coined the catalytic ring has been proposed in which two elastic pipelines flow in opposite directions while at the same time interacting with each other. We have currently began evaluations on autonomous distributed associative processing which is expected to play a fundamental role in our research toward highly parallel processing methodology to realize the next generation of knowledge processing. Less

Report

(4 results)
  • 1990 Annual Research Report   Final Research Report Summary
  • 1989 Annual Research Report
  • 1988 Annual Research Report
  • Research Products

    (43 results)

All Other

All Publications (43 results)

  • [Publications] 寺田 浩詔: "VLSI向きデ-タ駆動プロセッサ:Qーx" 電子情報通信学会論文誌(D). 8. 1383-1390 (1988)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Tsutomu SASAO: "On the optimal design of multipleーvalued PLA's" IEEE Trans.on Computer. 4. 582-592 (1989)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Shinji KOMORI: "The dataーdriven microprocessor" IEEE MICRO. 3. 45-59 (1989)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Shinji KOMORI: "A 40MFLOPS 32ーbit floatingーpoint processor with elastic pipeline scheme" IEEE Journal of SolidーState Circuit. 24. 1341-1347 (1989)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Hidehiro TAKATA: "A 100ーmegaーaccess per second matching memory for a dataーdriven microprocessor" IEEE Journal of SolidーState Circuit. 25. 95-99 (1990)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Shinji KOMORI: "A 50 MFLOPS superpipelined dataーdriven microprocessor" Proc.of International Solid State Circuit Conference. 38. 92-93,294 (1990)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] 寺田 浩詔: "“VLSI向きデ-タ駆動形プロセッサ:Qーx",bit 別冊『並列コンピュ-タア-キテクチャ』" 共立出版, 250(104-113) (1989)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Hiroaki NISHIKAWA: "“Architecture of a VLSIーoriented DataーDriven processor:The Qーv1" Advanced topics in dataーflow computing,Chapter9" PrinticeーHall,Inc., 626(247-264) (1991)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Hiroaki TERADA, et. al.: "A VLSI-oriented data-driven processor : Q-x" Trans. on IEICEJ. Vol. J71-D, no. 8. 1383-1390 (1988)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Shinji KOMORI, et. al.: "Evaluation of a circular-pipelined data-driven processor using Markov process model" Trans. on IEICEJ. vol. J71-D, no. 8. 1553-1559 (1988)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Hiroaki TERADA: "Prospects on communications terminals" J. of IEEJ. vol. 108, no. 8. 774-777 (1988)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Tsutomu SASAO: "Multiple-valued logic and optimization of programmable logic arrays" IEEE Computer. vol. 21, no. 4. 71-80 (1988)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Hiroaki TERADA, et. al.: "A VLSI-oriented data-driven processor : Q-x" Extra volume of bit : "Parallel Computer Architecture", Kyoritsu Shuppan. 104-113 (1989)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Hiroaki NISHIKAWA, et. al.: "Visual programming environment" J. of IPSJ. vol. 30, no. 4. 354-362 (1989)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Tsutomu SASAO: "On the optimal design of multiple-valued PLA's" IEEE Trans. on Comput.vol. 38, no. 4. 582-592 (1989)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Shinji KOMORI, et. al.: "The data-driven microprocessor" IEEE MICRO. vol. 3, no. 3. 45-59 (1989)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Hiroaki TERADA: "VLSI-oriented data-driven processors" J. of IEICEJ. vol. 72, no. 7. 742-749 (1989)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Tetsuo YAMASAKI, et. al.: "VLSI implementation of a variable-length pipeline scheme for data-driven processors" IEEE J. of Solid-State Circuits. vol. 24, no. 4. 933-937 (1989)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Shinji KOMORI, et. al.: "A 40MFLOPS 32-bit floating-point processor with elastic pipeline scheme" IEEE J. of Solid-State Circuits. vol. 24, no. 5. 1341-1347 (1989)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Hiroaki TERADA: "Perspective on telecommunication network in information society-Future of telecommunication network and its impact on information society" J. of IEICEJ. vol. 73, no. 1. 10-13 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Hidehiro TAKATA, et. al.: "A 100-mega-access per second matching memory for a data-driven microprocessor" IEEE J. of Solid-State Circuits. vol. 25, no. 1. 95-99 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Tsutomu SASAO: "On the complexity of MOD-2 Sum PLA's" IEEE Trans. on Comput.vol. 39, no. 2. 262-266 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Hiroaki TERADA: "Problems and future directions of communication software" J. of IEICEJ. vol. 74, no. 2. 104-108 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] Tsutomu SASAO: "Bounds on the average number of products in the minimum sum-of-products expressions for multiple-valued input two-output functions" IEEE Trans. on Comput.

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] 高田 英裕: "デ-タ駆動形プロセッサ用高速マッチングメモリ" 電子情報通信学会集積回路研究会. ICD90ー14. 51-57 (1990)

    • Related Report
      1990 Annual Research Report
  • [Publications] 西川 博昭: "超高位図的仕様記述環境(AESOP)の構想" 情報処理学会コンピュ-タア-キテクチャ研究会. ARCー83ー2. 7-12 (1990)

    • Related Report
      1990 Annual Research Report
  • [Publications] 西川 洋一郎: "超高位図的仕様記述環境(AESOP)のプロトタイプの開発" 情報処理学会コンピュ-タア-キテクチャ研究会. ARCー83ー3. 13-18 (1990)

    • Related Report
      1990 Annual Research Report
  • [Publications] Hiroaki NISHIKAWA: "Advanced Software Technologies Implementing Intelligent and UserーFriendly ServicesーTrends of Recent Research Activities" Proc.of International Conference on Communication Systems. 2. 11.2.1-11.2.5 (1990)

    • Related Report
      1990 Annual Research Report
  • [Publications] Shinji KOMORI: "A 50 MFLOPS superpipelined dataーdriven microprocessor" Proc.of International Solid State Circuit Conference. 38. 92-93,294 (1991)

    • Related Report
      1990 Annual Research Report
  • [Publications] 寺田 浩詔: "通信ソフトウェアの特徴と課題" 電子情報通信学会学会誌. 74. 104-108 (1991)

    • Related Report
      1990 Annual Research Report
  • [Publications] Komori,S: "The data-driven microprocessor" IEEE MICRO. 9-3. 45-59 (1989)

    • Related Report
      1989 Annual Research Report
  • [Publications] 寺田浩詔: "VLSI向きデ-タ駆動型プロセッサ" 電子情報通信学会誌. 72-7. 742-749 (1989)

    • Related Report
      1989 Annual Research Report
  • [Publications] Yamasaki,T.: "VLSI implementation of a variable-length pipeline scheme for data-driven processors" IEEE Journal of Solid-State Circuits. 24-4. 933-937 (1989)

    • Related Report
      1989 Annual Research Report
  • [Publications] Komori,S.: "A 40MFLOPS 32-bit floating-point processor with elastic pipeline scheme" IEEE Journal of Solid-State Circuits. 24-5. 1341-1347 (1989)

    • Related Report
      1989 Annual Research Report
  • [Publications] 寺田浩詔: "通信網の発展と情報化社会-通信網の将来展望と社会へのインパクト-" 電子情報通信学会誌. 73-1. 10-13 (1990)

    • Related Report
      1989 Annual Research Report
  • [Publications] Takata.H.: "A 100 mega-access per second matching memory for a data-driven microprocessor" IEEE Journal of Solid-State Circuits. 25-1. (1990)

    • Related Report
      1989 Annual Research Report
  • [Publications] 寺田浩詔: 電子情報通信学会論文誌(D). J71ーD,8. 1383-1390 (1988)

    • Related Report
      1988 Annual Research Report
  • [Publications] 小守伸史: 電子情報通信学会論文誌(D). J71ーD,8. 1553-1559 (1988)

    • Related Report
      1988 Annual Research Report
  • [Publications] 寺田浩詔: 電気学会雑誌. 108ー8. 774-777 (1988)

    • Related Report
      1988 Annual Research Report
  • [Publications] Yamazaki,T.: Proc.of VLSI circuits Symposium. 31-32 (1988)

    • Related Report
      1988 Annual Research Report
  • [Publications] Komori,K.: Proc.of International Solid-State Circuits Conference. 32. 46-47 (1989)

    • Related Report
      1988 Annual Research Report
  • [Publications] Komori,K.: MICRO. 9. (1989)

    • Related Report
      1988 Annual Research Report
  • [Publications] 寺田浩詔: "「並列コンピュータ・アーキテクチャ」VLSI向きデータ駆動形プロセッサ:Qーx" 共立出版, 43-52 (1989)

    • Related Report
      1988 Annual Research Report

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Published: 1988-04-01   Modified: 2016-04-21  

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