| Project/Area Number |
63850067
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| Research Category |
Grant-in-Aid for Developmental Scientific Research (B).
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | Osaka University |
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Principal Investigator |
TERADA Hiroaki Osaka University, Faculty of Engineering, Professor, 工学部, 教授 (80028985)
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| Co-Investigator(Kenkyū-buntansha) |
NISHIKAWA Hiroaki Osaka University, Faculty of Engineering, Research Associate, 工学部, 助手 (60180593)
SASAO Tsutomu Kyushu Institute of Technology, Faculty of Computer Science & System Engineering, 情報工学部, 助教授 (20112013)
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| Project Period (FY) |
1988 – 1990
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| Project Status |
Completed (Fiscal Year 1990)
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| Budget Amount *help |
¥7,400,000 (Direct Cost: ¥7,400,000)
Fiscal Year 1990: ¥1,800,000 (Direct Cost: ¥1,800,000)
Fiscal Year 1989: ¥1,800,000 (Direct Cost: ¥1,800,000)
Fiscal Year 1988: ¥3,800,000 (Direct Cost: ¥3,800,000)
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| Keywords | Ultra Parallel Algorithm / VLSI / Ultra Parallel Processing Scheme / Data-driven / Diagrammatical Language / Flow-thru Processing / Programmable Logic Array / Multiple Valued Logic / データ駆動 |
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| Research Abstract |
This research was initiated to realize the ultra parallel processing scheme on a VLSI chip by introducing the "flow-thru processing" concept. In order to establish a basis for highly parallel algorithms, we have undertaken such examples as the prime number generation (Sieve of Eratosthenes) in which high parallelisms existent in the target problem must execute without any side effects. We have shown that the elastic pipeline based upon the "flow-thru processing" concept is effective in exploiting such parallelisms (reference no. 1). Next, a single board data-driven processor system also based upon the "flow-thru processing" concept was realized and has served as a powerful experimental system. Using the system's monitoring facilities, we have confirmed the targeted performance of 20 MOPS (reference no. 3). Performance evaluations of 40 MFLOPS were exhibited for the system's ALU, the floating point processor (reference no. 4). Evaluations also confirmed 50 mega associations per second f
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or the firing control function (reference no. 5). Encouraged from these results, a prototype of the one chip data-driven processor was fabricated as an evaluation chip which yielded performance of 50 MFLOPS (reference no. 6).
Focusing upon the field programmability of programmable logic arrays, we have also began preliminary examination on variable structure elastic pipelines in order to realize a processor with more flexible capabilities.
When interconnected, such a powerful single processor can also serve as processing elements in large scale multiprocessor system which promises to achieve breakthroughs in performance thus far unsuccessful with conventional processors. An antonomous distributed parallel associative processor coined the catalytic ring has been proposed in which two elastic pipelines flow in opposite directions while at the same time interacting with each other. We have currently began evaluations on autonomous distributed associative processing which is expected to play a fundamental role in our research toward highly parallel processing methodology to realize the next generation of knowledge processing. Less
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