Grant-in-Aid for Developmental Scientific Research (B).
|Allocation Type||Single-year Grants|
|Research Institution||Kyoto University(1990)|
KAMBAYASHI Yahiko Kyoto Univ., Faculty of Eng., Professor, 工学部, 教授 (00026311)
WATANABE Masako Kyoto Univ., Faculty of Eng., Technical Assistant, 工学部, 教務技官 (70127158)
SAISHO Keizo Kyushu Univ., Faculty of Eng., Research Associate, 工学部, 助手 (50170486)
HIRAISHI Hiromi Kyoto Univ., Faculty of Eng., Associate Professor, 工学部, 助教授 (40093299)
MINO Michihiko Kyoto Univ., Faculty of Eng., Associate Professor, 工学部, 助教授 (70166099)
中村 千秋 長崎大学, 工学部, 助手 (00217861)
有川 正俊 九州大学, 工学部, 助手 (30202758)
古川 哲也 九州大学, 大型計算機センター, 講師 (00209165)
今井 浩 九州大学, 工学部, 助教授 (80183010)
田中 克己 神戸大学, 工学部, 助教授 (00127375)
|Project Period (FY)
1988 – 1990
Completed(Fiscal Year 1990)
|Budget Amount *help
¥21,300,000 (Direct Cost : ¥21,300,000)
Fiscal Year 1990 : ¥4,400,000 (Direct Cost : ¥4,400,000)
Fiscal Year 1989 : ¥7,700,000 (Direct Cost : ¥7,700,000)
Fiscal Year 1988 : ¥9,200,000 (Direct Cost : ¥9,200,000)
|Keywords||concurrency / hotspot / parallel transaction / backup / database / main memory database / recovery / log / ハ-ドウェア並行処理制御 / ハ-ドウェアバックアップ機構 / ホットスポットデ-タ / ハ-ドウェアログ / プロトタイピング / 並行処理制御 / ハ-ドウェア / シミュレ-ション / 2ポ-トメモリ / 大容量主記憶 / トランザクションマシン / ハードウェア / シミュレーション|
In the first year of this project, basic surveys on architectures and concurrency control mechanisms were initiated. In the next year, concurrency control for hotspot data were studied through simulations, and the hardware for the backup mechanism was designed. The final year was spent for implementation of the machine and publication of the results.
The major results are summarized as follows.
1) Theoretical studies were carried out on concurrency control mechanisms which can handle heterogeneous data and long term transactions under the serializability restricted with response time.
2) A new method was designed for concurrency control in database systems handling hotspot data and non-hotspot data separately, which had not been studied before.
3) A concurrency control mechanism for the parallel transaction model and its hardware implementation were studied. This research disclosed the problem of increased deadlocks in this architecture. A measure for this effect was proposed, and its hardware design was completed.
4) A continuously backuped memory was designed. Since the backup cost for hotspot data is expensive, research and development was initiated for a simultaneous hardware backup mechanism which does not slow down system operations. A continuously backuped disk unit was also designed. These mechanisms were integrated in the design of the target system which requires low overhead for backup.
5) A hardware logging system was designed. Since logging of database operations occupies nearly 50% of the total operation time of some systems, the hardware monitor for CPU buses is now under development.