| Project/Area Number |
63850083
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| Research Category |
Grant-in-Aid for Developmental Scientific Research
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| Allocation Type | Single-year Grants |
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| Research Field |
計測・制御工学
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| Research Institution | TOHOKU UNIVERSITY |
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Principal Investigator |
HIGUCHI Tatsuo TOHOKU UNIVERSITY, FACULTY OF ENGINEERING, PROFESSOR, 工学部, 教授 (20005317)
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| Co-Investigator(Kenkyū-buntansha) |
KANOMATA Akio SENDAI RADIO TECHNICAL COLLEGE, ASSOCIATE PROFESSOR, 助教授 (20044654)
KAMEYAMA Michitaka TOHOKU UNIVERSITY, FACULTY OF ENGINEERING, ASSOCIATE PROFESSOR, 工学部, 助教授 (70124568)
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| Project Period (FY) |
1988 – 1989
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| Project Status |
Completed (Fiscal Year 1989)
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| Budget Amount *help |
¥3,200,000 (Direct Cost: ¥3,200,000)
Fiscal Year 1989: ¥1,000,000 (Direct Cost: ¥1,000,000)
Fiscal Year 1988: ¥2,200,000 (Direct Cost: ¥2,200,000)
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| Keywords | Quaternary Complementary Pass Gate / Near-Neighbor Operation / Quaternary Logic System / Double Matching / Multiple-Valued Digital Processing / Quaternary CMOS Integrated Circuit / Quaternary OM Cell / Quaternary Image Processor / 4値PM・セル / ダブルパターンマッチング / パターンマッチングセル |
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| Research Abstract |
In this project a complementary pass gate ( CP-gate ) is proposed as a basic building block for a multiple-valued digital processing system. A CP-gate is composed of two pass transistors and a down literal circuit realized with multiple-level ion implants. The characteristic of the quaternary CP-gate is confirmed by simulation with SPICE2. The parameter used in the simulation are obtained from experiments of 10 mum CMOS process at Tohoku University. Consequently it is seen that the quaternary CP-gate has attractive features of high integration density and low power density.
As a practical application of the quaternary CP-gate, a image processor based on the pattern matching operation is designed and implemented. The image processing algorithm employed here is based on cellular logic operations which perform digitally to transform an array of 4-valued input data into a new data array. With image having 4-levels or colors, each pixel can be directly expressed by a single quaternary digit. The quaternary image processor presented here is based on the near-neighbor operations, and consists of the pattern matching (PM) cells using new double matching algorithm. Actually, the image processor for 3 x 3 near neighbor logic operation is fabricated in quaternary CMOS integrated circuits with 10 mum design rules at Tohoku University. As a result, a highly compact image processor can be realized because of the reduction of interconnections and double matching algorithm of the quaternary logic system using the quaternary CP-gates. Moreover, the image processor obtained is superior to a conventional binary processor in dissipation power and operation speed.
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