1991 Fiscal Year Final Research Report Summary
BASIC STUDY ON HIGH-PERFORMANCE MULTIPLE-VALUED SUPER CHIP FOR INTELLIGENT ROBOTS
| Project/Area Number |
01460157
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
計測・制御工学
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| Research Institution | TOHOKU UNIVERSITY |
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Principal Investigator |
HIGUCHI Tatsuo TOHOKU UNIVERSITY FACULTY OF ENGINEERING, 工学部, 教授 (20005317)
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| Co-Investigator(Kenkyū-buntansha) |
HANYU Takahiro TOHOKU UNIVERSITY FACULTY OF ENGINEERING PROFESSOR, 工学部, 助手 (40192702)
KAMEYAMA Michitaka PROFESSOR TOHOKU UNIVERSITY FACULTY OF ENGINEERING PROFESSOR, 工学部, 教授 (70124568)
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| Project Period (FY) |
1989 – 1991
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| Keywords | SD Number System / Multiple-Valued Bidirectional Current-Mode / SD Full-Adder / Modular Realization / SD Multiplier / Multiple-Valued Super Chip / ロボットビジョン用VLSI / 演算遅れ時間最小 |
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| Research Abstract |
In the conventional binary arithmetic circuits based on array structures, the operating speed is restricted by carry propagation. The carry propagation in the signed-digit (SD) number systems is always limited to one position to the left. However, the SD number systems have not been studied from the point of view of integrated circuit implementation.
This project begins with implementation of the multiple-valued bidirectional current-mode circuits composed of current source, current mirrors, threshold detector, and bidirectional current input. Using the bidirectional currentmode circuits, the SD full adder is realized. The layout of the SD full adder is given with 2-mum CMOS technology. The module is constructed by an adder, a partial-product generator, a quotient digit generator, a sign invertor, two encoders and four wiring blocks.
Using the modules thus obtained, any arithmetic operations based on addition, subtraction, multiplication and division can be realized by appropriately specifying the interconnection among the modules. This modular realization is very useful for semicustom VLSI as gate array. The comparison between the proposed SD multiplier and the fastest binary multiplier is carried out.
The SD multiply time is comparable to that of the fastest binary multiplier. From the point of view of reduction in design complexity, however, the SD multiplier is much more superior to the binary multiplier.
Lastly, it is demonstrated that these advantages of the multiple-valued technology are useful for implementation of the multiple-valued super chip for intelligent robots. The high-performance of the chip is also evaluated in detail.
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