1990 Fiscal Year Final Research Report Summary
Research on Development of a Logic Design Verification System Based on Time-Symbolic Simulation
| Project/Area Number |
01850074
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| Research Category |
Grant-in-Aid for Developmental Scientific Research (B).
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | Kyoto University |
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Principal Investigator |
YAJIMA Shuzo Kyoto Univ., Faculty of Engineering, Professor, 工学部, 教授 (20025901)
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| Co-Investigator(Kenkyū-buntansha) |
KAWAKUBO Kazuo Fukuyama Univ., Faculty of Engineering, Assoc. Professor, 工学部, 助教授 (10186067)
OGINO Hiroyuki Kyoto Univ., Faculty of Engineering, Staff, 工学部, 教務職員 (40144323)
ISHIURA Nagisa Kyoto Univ., Faculty of Engineering, Instructor, 工学部, 助手 (60193265)
TAKAGI Naofumi Kyoto Univ., Faculty of Engineering, Instructor, 工学部, 助手 (10171422)
HIRAISHI Hiromi Kyoto Univ., Faculty of Engineering, Assoc. Professor, 工学部, 助教授 (40093299)
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| Project Period (FY) |
1989 – 1990
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| Keywords | Logic Design Verification / Timing Verification / Logic Simulation / Symbolic Simulation / Logic Design / Asynchronous Sequential Circuit / Hazard |
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| Research Abstract |
We have carried out researches on development of a logic design verification system based on time-symbolic simulation and have got the following results.
1. Algorithms for Logic Design Verification
We have developed two methods for analyzing results obtained from time-symbolic simulation ; one is based on comparison of event-trees and the other is based on symbolic simulation of automaton that represents specification. We have also investigated the method for describing specification of digital systems using regular temporal logic.
2. Algorithms for Symbolic Simulation and Boolean Function Manipulation
We have developed an efficient method for Boolean function manipulation method based on a data structure named shared binary decision diagram so as to carry out simplification and comparison of Boolean formulas which is indispensable for time-symbolic simulation.
3. Implementation of a Time-Symbolic Simulation Software
We have carried out researches on improvements of algorithms for simulation and result analysis of time-symbolic simulation and have implemented a time-symbolic simulator and peripheral programs that construct a logic design verification system. The simulator can handle logic circuits up to 100 gates, including ones containing feedback loops.
4. Graphic Interface of the Logic Design Verification System
We have carried out researches on connection between workstations and a multi-computer multi-screen (MCMS) graphic system and data management, so as to develop a user interface of the logic design verification system.
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