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1990 Fiscal Year Final Research Report Summary

Implementation of an Ultra-Higyly Parallel Residue Arithemtic Integrated Circuit Based on Multiple-Vlaued Logic and its Evaluation

Research Project

Project/Area Number 01850085
Research Category

Grant-in-Aid for Developmental Scientific Research (B).

Allocation TypeSingle-year Grants
Research Field 計測・制御工学
Research InstitutionTohoku University

Principal Investigator

KAMEYAMA Michitaka  Tohoku University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (70124568)

Co-Investigator(Kenkyū-buntansha) TOMABECHI Nobuhiro  Hachinohe Institute of Technology, Faculty of Engineering, Professor, 工学部, 教授 (70048180)
Project Period (FY) 1989 – 1990
KeywordsSymmetric Residue Number System / Multiple-Valued Current-Mode Logic / Signed-Digit Arithmetic Circuit / Highly-Parallel Multiply Adder / Current-Mode CMOS Integrated Circuit / Residue Arithmetic VLSI
Research Abstract

This research discusses the implementation of a new residue arithmetic integrated circuit based on multiple-valued coding and multiple-valued bidirectional current-mode MOS technology. A new multiple-valued coded residue digit representation is introduced based on the pseudo-primitive root. With this coding, mod m multiplication and mod m addition can be executed using only shift and radix-5 signed-digit arithmetic operations, respectively. Furthermore, mod m multiplication by a constant coefficient can be performed simply by exchanging wire connections.
Multiple-valued bidirectional current-mode MOS technology is employed to implement the residue arithmetic circuit. In order to confirm the principle operations, the mod 7 three-operand multiply adder composed of 190 transistors has been designed and fabricated in 10-um CMOS design rule. The arithmetic circuit has a regular array structure which offers the potential for compact VLSI implementation.
Although residue arithmetic operations are restricted on integer arithmetic, the above high performance can hardly be achieved thorough the use of conventional binary arithmetic circuit. This highly parallel residue arithmetic chip will be of great use in many real-time applications such as robot systems.

  • Research Products

    (24 results)

All Other

All Publications (24 results)

  • [Publications] Michitaka Kameyama: "UltraーHighly Parallel Residue Arithmetic VLSI System" Digest of Technical Papers,1989 Symposium on VLSI Circuits. 127-128 (1989)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Shoji Kawahito: "HighーPerformance MultipleーValued Radixー2 SignedーDigit Multiplier and Its Application" Digest of Technical Papers,1989 Symposium on VLSI Circuits. 125-126 (1989)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 野村 昌弘: "多値SignedーDigit数演算モジュ-ルに基づくVLSIシステムの構成" 平成元年度電気関係学会東北支部連合大会講演論文集. 110 (1989)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 野村 昌弘: "配列型多値演算VLSIシステムの性能評価" 電子情報通信学会技術研究報告. ICD89ー120. 65-72 (1989)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Michitaka Kameyama: "Highly Parallel Residue Arithmetic Chip Based on MultipleーValued Bidiretional CurrentーMode Logic" IEEE Journal of SolidーState Circuits. 24. 1404-1411 (1989)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 宋 奎翼: "相補型パスゲ-トに基づく4値順序回路の構成" 電子情報通信学会論文誌Dー1. J72ーDーI. 837-844 (1989)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Shoji Kawahito: "MultipleーValued Radixー2 SignedーDigit Arithmetic Cirucuits for HighーPerformance VLSI Systems" IEEE Journal of SolidーState Circuits. 25. 125-131 (1990)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 野村 昌弘: "多値SignedーDigit数演算モジュ-ルに基づくデ-タ駆動形アレ-の構成" 平成2年電子情報通信学会春季全国大会講演論文集. 5-219 (1990)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 魏書 剛: "多値RSA暗号処理VLSIの性能評価" 電子情報通信学会論文誌Dー1. J73ーDーI. 484-491 (1990)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Michitaka Kameyama: "Toward the Age of BeyondーBinary Electronics and Systems" Proceedings of the 1990 IEEE International Symposium on MultipleーValued Logic. 162-166 (1990)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Michitaka Kameyama: "Modular Design of MultipleーValued Arithmetic VLSI System Using SignedーDigit Number System" Proceedings of the 1990 IEEE International Symposium on MultipleーValued Logic. 355-362 (1990)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 藤岡 与周: "マニピュレ-タ逆ヤコビ剰余数演算システムの構成" 平成2年度電気関係学会東北支部連合大会講演論文集. 265 (1990)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 藤岡 与周: "剰余数系に基づくマニピュレ-タ擬似逆ヤコビ演算プロセッサの構成" 計測自動制御学会東北支部第123回研究集会資料. 123ー7. (1990)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 野村 昌弘: "SignedーDigit数演算多値モジュ-ルアレ-とロボット制御用VLSIプロセッサ設計への応用" 電子情報通信学会技術研究報告. ICD90ー139. 9-16 (1990)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 亀山 充隆: "SignedーDigit数演算多値モジュ-ルアレ-の構成" 電子情報通信学会論文誌A. J74ーA. 296-303 (1991)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] M. Kameyama, T. Sekibe and T. Higuchi: "Ultra-Highly Parallel Residue Arithmetic VLSI System" Digest of Technical Papers, 1989 Symposium on VLSI Circuits, Kyoto. 127-128 (1989)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] S. Kawahito, M. Kameyama and T. Higuchi: "High-Performance Multiple-Valued Radix-2 Signed-Digit Multiplier and Its Application" Digest of Technical Papers, 1989 Symposium on VLSI Circuits, Kyoto. 125-126 (1989)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] M. Kameyama, T. Sekibe and T. Higuchi: "Highly Parallel Residue Arithmetic Chip Based on Multiple-Valued Bidirectional Current-Mode Logic" IEEE Journal of Solid-State Circuits. vol. 24, no. 5. 1404-1411 (1989)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. I. Sohng, M. Kameyama and T. Higuchi: "Design of Sequential Logic Circuits Based on Quaternary Complementary Pass Gates" IEICE Transactions D-I. vol. J72-D-I, no. 12. 837-844 (1989)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] S. Kawahito, M. Kameyama and T. Higuchi: "Multiple-Valued Radix-2 Signed-Digit Arithmetic Circuits for High-Performance VLSI Systems" IEEE Journal of Solid-State Circuits. vol. 25, no. 1. 125-131 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] S. Wei, M. Kameyama and T. Higuchi: "Performance Evaluation of a Multiple-Valued RSA Encryption VLSI" IEICE Transaction D-I. vol. J73-D-I, no. 5. 484-491 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] M. Kameyama: "Toward the Age of Beyond-Binary Electronics and System" Proceedings of the IEEE International Symposium on Multiple-Valued Logic, Charlotte. 162-166 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] M. Kameyama, M. Nomura and T. Higuchi: "Modular Design of Multiple-Valued Aritmemtic VLSI System Using Signed-Digit Number System" Proceedings of the IEEE International Symposium on Multiple-Valued Logic, Charlottte. 355-362 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] M. Kameyama, M. Nomura and T. Higuchi: "Design of Multiple-Valued Module Array Using Signed-Digit arithmetic" IEICE Transactions A. vol. J74-A, no. 2. 296-303 (1991)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 1993-08-12  

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