1992 Fiscal Year Final Research Report Summary
Studies on Functional Memory Type Parallel Processor Architectures and Their Massively Parallel Algorithms.
| Project/Area Number |
02452160
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | KYOTO UNIVERSITY |
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Principal Investigator |
TAMARU Keikichi Kyoto Univ., Faculty of Engineering, Professor, 工学部, 教授 (10127102)
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| Co-Investigator(Kenkyū-buntansha) |
ONODERA Hidetoshi Kyoto Univ., Faculty of Engineering, Assoc. Professor, 工学部, 助教授 (80160927)
YASUURA Hiroto Kyushu Univ., Interdisciplinary Graduate School of Enging. Sci., Prof., 大学院総合理工学研究科, 教授 (80135540)
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| Project Period (FY) |
1990 – 1992
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| Keywords | Functional Memory Type Parallel Processor Architecture / FMPP / Content Addressable Memory / Functional Memory / Massively Parallel Algorithm / SIMD / Massively Parallel Computation / Massively Parallel Processing |
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| Research Abstract |
We have made an in-depth study on a parallel processor architecture called FMPP (Functional Memory Type Parallel Processor Architecture) and massively parallel algorithms on FMPP. Results are summarized as follows.
(1) Studies on Massively Parallel Computation Capability of FMPP: Introduction of some computational power inside memory circuits enables FMPP to realize a highly parallel computation in the memory circuits.
(2) Studies on Integrated Circuit Technology for FMPP: Based on the recent technology trend of a CAM LSI which is the principal component of FMPP, Integration scale of CAM LSIs in 0.8 mum CMOS technology is predicted to be 100 Kbit with SRAM cells and 400 Kbit with DRAM cells. In 0.5 mum technology, it will reach 1 Mbit with DRAM cells
(3) Studies on a new FMPP architecture: A new architecture of FMPP called bit-parallel block-parallel (BPBP) FMPP has been proposed. So far, a bit-serial word-parallel (BSWP) implementation based on a CAM is mainly considered as one of promising architectures of FMPP. The BSWP FMPP achieves massively parallel computation in a reasonable hardware amount. It however does not allow operations between two words, which restriction limits the the applicability of the BSWP FMPP. The BPBP is designed to execute logical and arithmetic operations on two words. These operations are performed simultaneously on every group of words call a block. BPBP FMPP hereby achieves a high performance while maintaining high integration density of the BSWP, and in suitable for various applications.
(4) Studies on massively parallel algorithms for FMPP: We have developed various parallel algorithms for FMPP which has a highly parallel SIMD computation scheme. The targets of the algorithms include pattern matching, the shortest path problem, logic simulation, intersection calculation of lines, ray tracing, and neural network simulation.
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