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1992 Fiscal Year Final Research Report Summary

Development of A Silicon Complilation System for Rewritable LSIs

Research Project

Project/Area Number 02555073
Research Category

Grant-in-Aid for Developmental Scientific Research (B)

Allocation TypeSingle-year Grants
Research Field 情報工学
Research InstitutionKyushu Institute of Technology

Principal Investigator

SASAO Tsutomu  Kyushu Institute of Technology Department of Computer Science and Technology, Associate Professor, 情報工学部, 助教授 (20112013)

Co-Investigator(Kenkyū-buntansha) KODA Norio  Tokuyama College of Technology Department of Computer Science and Technology, Pr, 情報電子工学科, 教授 (10099864)
SASAO Tsutomu  Kyushu Institute of Technology Department of Computer Science and Electronics, A (20112013)
Project Period (FY) 1990 – 1992
KeywordsProgrammable Gate Array / Binary Decision Diagrams / Functional Decomposition / Multi-level Logic Synthesis / Reed-Muller Expansion
Research Abstract

Field programmable gate arrays (FPGAs) are devices that can be programmed by the user to implement a logic function. Because of short turnaround time, they are becoming increasingly important for rapid prototyping. In addition, they are inexpensive to manufacture. All FPGA architectures consist of repeated arrays of identical logic blocks. A logic block is a versatile configuration of logic elements that can be programmed by the user. The interconnections for the circuit are also programmed. Among various FPGA architectures, we consider the Look up table(LUT) type FPGA where each logic block can realize an arbitrary 5 variable function. In such a FPGA., both logic bloc ks and the interconnections are programmable.
In this research, we developed a method for designing LUT type FPGAs by functional decomposition. LUT type FPGAs consists of 5-input LUTs. The outline of the method is 1) Find a decomposition of the form f=g (h(X1),X2), where X2 contains two variables, and the column multiplicities are equal to or less than 8. We have developed an efficient way to find such a decomposition by using Binary Decision Diagrams (BDDs). A function whose column multiplicity is equal to or less than eight is realized by a network for h(X1) with three outputs, followed by a 5-input LUT. The LUT has three inputs from the network for h(X1), and two inputs for X2.2) Decompose the functions recursively until the functions can be realized by 5-input LUTs. This algorithm produced solutions competitive to the previously published methods. Produced networks have regular interconnections, and easily implemented by FPGAs.
As a design method for FPGAs, we also developed a design method for AND-EXOR circuits. In many cases, AND-EXOR circuits require fewer connections and gates than AND-OR circuits to realize same function.

  • Research Products

    (30 results)

All Other

All Publications (30 results)

  • [Publications] T. Sasao: "EXMIN. A simplification algorithm for exclusive-or sum-of-products expressions for multiple-valued input two-valued output functions" International Symposium on Multiple-Valued Logic, Charlotte, North Carolina. 128-135 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao and D. Brand: "A non-deterministic algorithm for minimizing AND-EXOR logical expressions" National Convention of IEICE Japan. SA-3-2. (1990)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N. Koda and T. Sasao: "On the simplification of 5-variable AND-EXOR expressions" National Convention of IEICE Japan. SA-3-3. (1990)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao: "Exclusive-Or sum-of-products expressions: their properties and minimization algorithms" IEICE Technical Paper. VLD90-87. (1990)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao and D. Brand: "On the minimization of AND-EXOR expressions" IEICE Technical Paper. VLD90-88. (1990)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N. Koda and T. Sasao: "On the number of product terms of 6-variable AND-EXOR minimum expressions,(in Japanese)" National Convention of IEICE Japan. A-120. (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N. Koda and T. Sasao: "AND-EXOR expressions and their equivalence classes,(in Japanese)" National Convention of IEICE Japan. A-119. (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao and N. Koda: "Some classes of AND-EXOR expressions and their complexity,(in Japanese)" IEICE Technical paper. Vol.MVL91-4. (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao: "Bounds on the average number of products in the minimum sum-of-products expressions for multiple-valued input two-valued output functions" IEEE Trans. on Comput. Vol.40,No. 5. 645-651 (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] D. Brand and T. Sasao: "On the minimization of AND-EXOR expressions" International Workshop on Logic Synthesis, Research Triangle Park, NC. (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao: "A transformation of multiple-valued input two-valued output functions and its application to simplification of exclusive-or sum-of-products expressions" International Symposium on Multiple-Valued Logic,. 270-279 (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao: "On the complexity of some classes of AND-EXOR expressions" Research Report of Institute of Mathematical Analysis, Kyoto University. (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N. Koda and T. Sasao: "On the number of product terms of AND-EXOR minimumexpressions,(in Japanese)" IEICE Technical paper. FTS91-22. (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao: "On the complexity of some classes of AND-EXOR expressions" IEICE Technical paper. FTS91-35. (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N. Koda and T. Sasao: "Four variable AND-EXOR minimum expressions and their properties,(in Japanese) Trans" IEICE Japan. Vol. K74-D-1, No. 11. 765-773 (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao: "Optimization of multiple-valued AND-EXOR expressions using multiple-place decision diagrams" IEICE Technical Paper. VLD91-109. (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N. Koda and T. Sasao: "An upper bound on the number of product terms in AND-EXOR minimum expressions,(in Japanese)" Trans. IEICE Japan. Vol.J75-D-1,No.3. 135-142 (1992)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao: "EXMIN2: A tool for EXOR logic synthesis" Proceedings of the Synthesis and Simulation Meeting and International Interchange. APRIL. 06. 46-53 (1992)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao: "Optimization of multiple-valued AND-EXOR expressions using multiple-place decision diagrams" ISMVL-92. 451-458 (1992)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao: "FPGA Design by Generalized Functional Decomposition" International Symposium on Logic Synthesis and Microprocessor Architecture. July 12-15. 154-161 (1992)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao and Jon T. Butler: "On the Analysis of an FPGA Architecture" International Symposium on Logic Synthesis and Microprocessor Architecture. July 12-15. 162-168 (1992)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao and T. Amada: "Optimization of AND-EXOR Expressions using Ternary Decision Diagrams," International Symposium on Logic Synthesis and Microprocessor Architecture. July 12-15. 200-205 (1992)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao and T. Amada: "A Design Method of AND-OR-EXOR Circuits" International Symposium on Logic Synthesis and Microprocessor Architecture. July 12-15. 206-213 (1992)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao (ed.): "Logic Synthesis and Optimization" Kluwer Academic Publishers. (1993)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N. Koda and T. Sasao: "A minimization method for AND-EXOR expressions using lower bonds theorem,(in Japanese)" Trans, IEICE Japan. Vol. J76-D-1, No.1. 1-10 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao, and T. Amada: "A method to generate prime implicants using ternary decision diagrams, "(in Japanese)" IEICE Technical Paper. FTS92-74. (1993)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N. Koda and T. Sasao: "LP characteristic vector of logic function and its application to the minimization of AND-EXOR expressions,(in Japanese)" IEICE Technical Paper. FTS92-75. (1993)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao: "Optimization of pseudo-Kronecker expressions using multiple-place decision diagrams" IEICE Transactions on Information and Systems. (1993)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Sasao: "EXMIN2: A simplification algorithm for exclusive-OR-Sum-of-products expressions for multiple-valued input two-valued output functions" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Daniel Brand and t. Sasao: "Minimization of AND-EXOR expressions using rewriting rules," IEEE Transactions on Computers.

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 1994-03-24  

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