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1991 Fiscal Year Final Research Report Summary

Research on High-Level Information Extraction in Integrated Circuit Design

Research Project

Project/Area Number 02650264
Research Category

Grant-in-Aid for General Scientific Research (C)

Allocation TypeSingle-year Grants
Research Field 情報工学
Research InstitutionKyoto University

Principal Investigator

YASUURA Hiroto  Kyoto Univ., Faculty of Engineering, Assoc. Professor, 工学部, 助教授 (80135540)

Co-Investigator(Kenkyū-buntansha) ONODERA Hidetoshi  Kyoto Univ., Faculty of Engineering, Research Assoc., 工学部, 助手 (80160927)
TAMARU Keikichi  Kyoto Univ., Faculty of Engineering, Professor, 工学部, 教授 (10127102)
Project Period (FY) 1990 – 1991
KeywordsLogic Synthesis / Design Verification / Functional Information Extraction / Arithmetic Functions / Sequential Circuits / Combinational Logic Circuits / Binary Decision Diagram / Functional Level Simulation
Research Abstract

The goal of this research project is to establish a basic meibodology for functional infoffnadon extraction from logic circuits. The target problem is inverse transformation of logic synthesis. The obtained results of this research are summarized as follows :
1. We developed a method to extract furiclional information from combinational logic circuits. In this method, we use a Binary Decision Diagram(BDD)as a basic data structure. We also use additional information added to a net list of a logic circuit. The additional information consists of types of signal lines and coding scheme of numerical data and characters. Using the additional information. we can extract arithmetic functions like addition or multiplication, as well as logical operations. Our approach is independent from structure of a circuit from which functional information is extracted. We developed a prototype system of functional information extraction, called FINES, and extend the method to functional information extraction from sequential circuits.
2. We developed a system to extract functional information from descriptions of transister level circuits. Combining the established technology to extract circuits from layout information, we can develop a system to extract functional information from layout descriptions. This method is independent from libraries of logic elements.
3. We discussed applications of the functional information extraction technique to automatic generation of functional simulation models, design verification, test generation and computer aided documentation.
All the above results have been published or presented in journals, international conferences and workshops. The methodology developed in the research can be applied to analog circuits and software engineering area. The fundamental problem of fundonal information extraction is recognition of the function or behavior from static descriptions. This seems to be one of the basic problems of inforinadon sciences.

  • Research Products

    (12 results)

All Other

All Publications (12 results)

  • [Publications] Masahiko Ohmura: ""Extraction of Arithmetic Functions from Combinational Circuits"" Proceedings of the Synthesis and Simulation Meeting and International Interchange SASIMI'90. 40-47 (1990)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Masahiko Ohmura: ""Extraction of Functional Information from Combinational Circuits"" Digest of Technical Papers,IEEE International Conference on Computer-Aided Disign (ICCD-90). 176-179 (1990)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 唐津 修: "“論理合成時代のハ-ドウェア設計用準言語:UDL/I"" 電子情報通信学会論文誌. J74ーA. 170-178 (1991)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 大村 昌彦: "“組合せ回路の機能情報抽出"" 電子情報通信学会論文誌. J74ーA. 247-255 (1991)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 大村 昌彦: "“同期式順序回路の機能情報抽出"" 第4回回路とシステム軽井沢ワ-クショップ論文集. 52-56 (1991)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 淡海 功二: "“UDL/Iのセマンティック定義に基づく可変精度シミュレ-タの試作"" 第4回回路とシステム軽井沢ワ-クショップ論文集. 57-62 (1991)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Masahiko Ohmura, Hiroto Yasuura and Keikichi Tamaru: ""Extraction of Arithmetic Functions from Combinational Circuits"" Proceedings of the Synthesis and Simulation Meeting and International Interchange. SASIMI'90. 40-47 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Masahiko Ohmura, Hiroto Yasuura and Keikichi Tamaru: ""Extraction of Functional Information from Combinational Circuits"" Digest of Technical Papers, IEEE International Conference on Computer-Aided Design. ICCAD-90. 176-179 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Osamu Karatsu, Tamio Hoshino, Nagisa Ishiura and Hiroto Yasuura: ""UDL/I : A Hardware Design Language Standard for Logic Synthesis Age"" Transactions of the IEICE. J74-A, NO. 2. 170-178 (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Masahiko Ohmura, Hiroto Yasuura and Keikichi Tamaru: ""Functional Information Extraction from Combinational circuits"" Transactions of the IEICE. J74-A, NO. 2. 247-255 (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Masahiko Ohmura, Hiroto Yasuura and Keikichi Tamaru: ""Extraction of Functional Information from Synchronous Sequential Circuits"" Proceedings of the 4-th Karuizawa workshop on Circuits and Systems. 52-56 (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Masahiko Ohmura, Hiroto Yasuura and Keikichi Tamaru: ""Extraction of Functional Information from Sequential Circuits"" IPSJ SIGDA Report. DA-60-12. (1991)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 1993-03-16  

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