1991 Fiscal Year Final Research Report Summary
Research on High-Level Information Extraction in Integrated Circuit Design
| Project/Area Number |
02650264
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | Kyoto University |
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Principal Investigator |
YASUURA Hiroto Kyoto Univ., Faculty of Engineering, Assoc. Professor, 工学部, 助教授 (80135540)
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| Co-Investigator(Kenkyū-buntansha) |
ONODERA Hidetoshi Kyoto Univ., Faculty of Engineering, Research Assoc., 工学部, 助手 (80160927)
TAMARU Keikichi Kyoto Univ., Faculty of Engineering, Professor, 工学部, 教授 (10127102)
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| Project Period (FY) |
1990 – 1991
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| Keywords | Logic Synthesis / Design Verification / Functional Information Extraction / Arithmetic Functions / Sequential Circuits / Combinational Logic Circuits / Binary Decision Diagram / Functional Level Simulation |
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| Research Abstract |
The goal of this research project is to establish a basic meibodology for functional infoffnadon extraction from logic circuits. The target problem is inverse transformation of logic synthesis. The obtained results of this research are summarized as follows :
1. We developed a method to extract furiclional information from combinational logic circuits. In this method, we use a Binary Decision Diagram(BDD)as a basic data structure. We also use additional information added to a net list of a logic circuit. The additional information consists of types of signal lines and coding scheme of numerical data and characters. Using the additional information. we can extract arithmetic functions like addition or multiplication, as well as logical operations. Our approach is independent from structure of a circuit from which functional information is extracted. We developed a prototype system of functional information extraction, called FINES, and extend the method to functional information extraction from sequential circuits.
2. We developed a system to extract functional information from descriptions of transister level circuits. Combining the established technology to extract circuits from layout information, we can develop a system to extract functional information from layout descriptions. This method is independent from libraries of logic elements.
3. We discussed applications of the functional information extraction technique to automatic generation of functional simulation models, design verification, test generation and computer aided documentation.
All the above results have been published or presented in journals, international conferences and workshops. The methodology developed in the research can be applied to analog circuits and software engineering area. The fundamental problem of fundonal information extraction is recognition of the function or behavior from static descriptions. This seems to be one of the basic problems of inforinadon sciences.
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