1991 Fiscal Year Final Research Report Summary
Parallel Processing system Based on Asynchronous Relaxization
| Project/Area Number |
02650275
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | Waseda University |
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Principal Investigator |
MURAOKA Yoichi Waseda Univ. School of Science and Engineering, Professor, 理工学部, 教授 (50182085)
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| Project Period (FY) |
1990 – 1991
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| Keywords | Parallel Processing / Compiler |
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| Research Abstract |
The major results of this research include the followings.
(1)The deign and implimentation of the precedence activation scheme
As it is well known, it has been very difficult to extract parallelsim from a program with many jump instructions. The proposed scheme evaluates all possible computations simultaneously, and later select the one which is valid. The scheme was implemented in the context of dataflow cotrol mechanism.
(2)The design of a parallel compiler
A parallel compiler which takes a program written in an ordinary language, and comiples it onto a complex of machines such as a vector machine and an array machine. Further, a more efficient compiling technique for for loops which expands a compound loop into a single loop was proposed.
(3)The design and implimentation of a parallel fineite element solver
A parallel fineite element solver which maps a problem efficiently on an array machine has been proposed and implimented.
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