1991 Fiscal Year Final Research Report Summary
Research on Wafer Scale Integrated Computer
| Project/Area Number |
02805042
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | Faculty of Engineering, Tohoku University |
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Principal Investigator |
HORIGUCHI Susumu Faculty of Engineering, Tohoku University, Associate Professor, 工学部, 助教授 (60143012)
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| Co-Investigator(Kenkyū-buntansha) |
SHIMODAIRA Hiroshi Faculty of Engineering, Tohoku University, Research Associate, 工学部, 助手 (30206239)
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| Project Period (FY) |
1990 – 1991
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| Keywords | Massively Parallel Computer / Integrated Circuit / Redundancy Architecture / Wafer Scale System / Fault Tolerance |
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| Research Abstract |
Since the integarted circuit was invented, researches and designers have been challenging to get much more circuits on a chip. Wafer Scale Integration(WSI)is one of promising technologies for developing massively parallel systems which satisfy the continuous increasing demand for computer power.
The aim of this research is to study a novel architecture of Wafer Scale Computer. We already proposed hybrid systolic sorters which are suitable for WSI implementation. The hybrid sorter has a hierarchical redundancy network and is powerful architecture for fault tolerance. We also proposed a reconfigurable architecture for mesh-interconnection processing arrays. Our WSI architecture of array processors achieves both higher reliability and higher production yield.
We have studied on WSI architectures of cube-connected cycle multiprocessor. Cube-connected cycle is one of promising network topologies for multiprocessor systems. Our placement scheme of processing elements performs higher yield than other schemes. Testing and testability in WSI systems is still remained problems.
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