1991 Fiscal Year Final Research Report Summary
Logic synthesis using EXOR gates
| Project/Area Number |
02805046
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | Kyushu Institute of Technology |
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Principal Investigator |
SASAO Tsutomu Kyushu Institute of Technology Department of Computer Science and Technology, Associate Professor, 情報工学部, 助教授 (20112013)
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| Co-Investigator(Kenkyū-buntansha) |
神田 徳夫 徳山工業高等専門学校, 情報電子工学科, 助教授 (10099864)
SASAO Tsutomu Kyushu Institute of Technology Department of Computer Science and Technology, As (20112013)
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| Project Period (FY) |
1990 – 1991
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| Keywords | Logic Design / AND-EXOR Circuits / Logic Minimization / Multi-Level Logic Synthesis / Reed-Muller Expansion / 多段論理回路 / 論理合成 |
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| Research Abstract |
Automatic logic synthesis tools are extensively used in LSI design. Most logic synthesis tools use AND and OR gates as basic logic elements. Arithmetic and error correcting circuits can be realized with many fewer gates if EXOR gates are available as well as AND and OR gates. Such circuits can be derived from AND-EXOR two-level circuits. So the minimization of Exclusive-OR sum-of-products expressions(ESOPs), which corresponds to the minimization of AND-EXOR two-level circuits, is important. ESOPs require fewer products than SOPs to realize randomly generated functions and symmetric functions. To realize an arbitrary function of 6 variables, an ESOP requires only 16 products, whereas an SOP requires 32 products. Although there exists a class of functions whose ESOP realizations require more production SOPS, the ESOP's are important tool in efficient logic design. The number of products in AND-OR two-level circuits can be reduced by adding decoders to the inputs(i. e., AND-OR PLAs with t
… More
wo-bit decoders). In a similar way, the number of products in AND-EXOR two-level circuits can be reduced by adding decoders to the inputs(i. e., AND-EXOR PLAs with two-bit decoders). We compared the number products and literals to represent arithmetic functions of 8-inputs by AND-OR circuits and AND-EXOR circuits with one and two-bit decoders, where a one-bit decoder generates true and complemented variables. Circuits based on ESOPs required fewer gates than the ones based on SOPS. The minimization of AND-EXOR circuits with decoders can be done by the minimization of ESOPs with multiple-valued inputs.
The first result is EXMIN2, a heuristic simplification algorithm for AND-EXOR expression with multiple-valued inputs. The algorithm iteratively reduces the number of the products in ESOPs as the first objective, and then reduces the number of the literals as the second objectives. Experimental results show that ESOPs usually require fewer products and connections than SOPs to represent arithmetic functions. The-second result is a design method for AND-OR-EXOR circuits. In the most technologies, EXORs are more expensive than ORs. To reduce the cost, we developed a method to replace some of the EXORs with ORs in ESOPs without increasing the number of the products. Less
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