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1993 Fiscal Year Final Research Report Summary

Studies on CAD system of Application Specific VLSI Circuits for Signal Processing

Research Project

Project/Area Number 03452174
Research Category

Grant-in-Aid for General Scientific Research (B)

Allocation TypeSingle-year Grants
Research Field 情報工学
Research InstitutionWaseda University

Principal Investigator

SHIRAI Katsuhiko  professor School of Science and Engineering, Waseda University, 理工学部, 教授 (10063702)

Co-Investigator(Kenkyū-buntansha) TAKEZAWA Toshiyuki  ATR Interpreting Telephony Research Laboratories
KASAHARA Hironori  associate professor school of Science and Engineering, Waseda University, 理工学部, 助教授 (30152622)
KOBAYASHI Tetsunori  associate professor School of science and Engineering, Waseda University, 理工学部, 助教授 (30162001)
MATSUMOTO Takashi  professor School of Science and Engineering, Waseda University, 理工学部, 教授 (80063767)
AKIZUKI Kageo  professor School of Science and Engineering, Waseda University, 理工学部, 教授 (10063603)
Project Period (FY) 1993
Keywordsdesign automation / ASIC / USIC / high-level synthesis / algorithm description / structural description / hardware description language / digital signal algorithm
Research Abstract

We have already researed the VLSI design system (SYARDS) based on high-level description for 5 years before this project. Besides, This system was evaluated through a connection with the existing VLSI ligic-level synthesis tool. The connection showed possibilities of the high-level synthesis systems like SYARDS.In this project, this system is advanced and generalized in order to implement the system including the design environment, which aims not only processor design but also its application. Moreover, this project is proceeded for the purpose of founding the high-level design technology. Definitely, we deal with problems on the improvement of the specification description language including concurrent processings, its analysis system, and the scheduling and simulator in operation level.
As another subject in the project, the design of a double layr parallel network is considered. This research is carried out by Takashi Matsumoto, and important results on a layred architecture for reg … More ularization neuro chips are acquired.
The application specification processors which executes the algorithms described in high-level languages (Pascal or C) can automatically be designed using the design system (SYARDS). For 3-year term of project, we strengthen the performance of SYARDS through the optimal design method using the extraction of local parallelism including algorithms, the support technology for bit-width determination, which is needed in dealing with the realistic algorithms for digital signal processing, the introduction of concurrent processing description with C language, and the optimization on the pipeline designs.
During the term of project, the concept of co-design is indicated in processor design which considers from both sides of hardware and software. However, this system is originally characterized to design compilers which generate its software as well as hardware. Therefore, this project is also close to the methodology of co-design.
In the future, SYARDS will be extended to the direction like this, and the results of this project are considered to have a great deal of significance for the future VLSI design technology. Less

  • Research Products

    (18 results)

All Other

All Publications (18 results)

  • [Publications] 池永 剛,白井 克彦: "“高級言語により記述されたアルゴリズムを実現する専用プロセッサ設計支援システム"" 情報処理学会論文誌. 32. 1445-1456 (1991)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] H.Kitabatake,K.Shirai: "“Functional Design of a Special Purpose Processor Based on High Level Specification Description"" IEICE Trans.Fundamentals,Vol.E75-A. 10. 1182-1190 (1992)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] H.Kobayashi,T.Matsumoto,T.Yagi and T.Shimmi: ""Image Processing Regularization Filters on Layered Architecture"" Neural Networks. 6. 327-350 (1993)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] T.Matsumoto and K.Kondo: ""Realization of the Weak Rod by a Double Layer Parallel Network"" Neural Computation.

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 北畠 宏信,白井 克彦: "“高位仕様記述からの専用プロセッサ設計における機能設計について"" 情報処理学会研究報告第60回設計自動化研究会. 25-32 (1991)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 雨坪 考尚,上田 穰,吉田 裕,白井 克彦: "“ビット幅を考慮した大規模システム処理系の設計手法について"" 情報処理学会設計自動化研究会. 67-2. (1993)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] H.Kobayashi,T.Matsumoto,T.Yagi and T.Shimmi: ""A Layered Architecture for Regularization Neuro Chips"" Proc.of IJCNN 91. (1991)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] T.Yagi,T.Matsumoto,Y.Funahashi,H.Kobayashi and T.Shimmi: ""The retina:a model of novel image processing device"" Proc.of the Korean Neural Network Conf.85. (1992)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] T.Matsumoto and K.Kondo: ""Weak Rod by a Double Layer Parallel Network"" Proc.of IJCNN 93. (1993)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] T.Ikenaga and K.Shirai: ""Design System for Special Purpose Processor Executing Algorithms Described by Higher Levell Language"" The Journal of the Information Processing Society of Japan. vol.32. 1145-1456 (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H.Kitabatake and K.Shirai: ""Functional Design of a Special Purpose Processor Based on High Level Specification Description"" IEICE Trans.Fundamentals. Vol.E75-A, No.10. 1182-1190 (1992-10)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H.Kobayashi, T.Matsumoto, T.Yagi and T.Shimmi: ""Image Processing Regularization Filters on Layred Architecture"" Neural Networks. vol.6. 327-350 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T.Matsumoto and K.Kondo: ""Realization of the Weak Rod by a Double Layr Parallel Network"" Neural Computation. (accepted).

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H.Kitabatake and K.Shirai: ""Functional Design in Special Purpose Processor Design from High Level Specification Description"" Proceedings of the 60th Conference on Design Automation of the Information Processing Society of Japan. 25-32 (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T.Amatsubo, Y.Ueda, Y.Yoshida and K.Shirai: ""Towards a Design Method for VLSI Considering Bit Width"" Proceedings of the Conference on Design Automation of the Information Processing Society of Japan. 67-2 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H.Kobayashi, T.Matsumoto, T.Yagi and T.Shimmi: ""A Layred Architecture for Regularization Neuro Chips"" Proceeding of IJCNN. 91. (1991)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T.Yagi, T.Matsumoto, Y.Funahashi, H.Kobayashi and T.Shimmi: ""The retina : a model of novel image processing device"" Proceeding of the Korean Neural Network Conference. 85. (1992)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T.Matsumoto and K.Kondo: ""Weak Rod by a Double Layr Parallel Network"" Proceedings of IJCNN. 93. (1993)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 1995-03-27   Modified: 2020-09-28  

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