1992 Fiscal Year Final Research Report Summary
IMPLEMENTATION OF ULTRA-HIGH-SPEED INFERENCE HARDWARE ENGINE BASED ON 4-VALUED CMOS INTEGRATED CIRCUITS AND ITS APPLICATION
| Project/Area Number |
03555082
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| Research Category |
Grant-in-Aid for Developmental Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
計測・制御工学
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| Research Institution | TOHOKU UNIVERSITY |
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Principal Investigator |
HIGUCHI Tatsuo TOHOKU UNIVERSITY FACULTY OF ENGINEERING PROFESSOR, 工学部, 教授 (20005317)
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| Co-Investigator(Kenkyū-buntansha) |
HANYU Takahiro TOHOKU UNIVERSITY FACULTY OF ENGINEERING ASSOCIATE PROFESSOR, 工学部, 助教授 (40192702)
KAMEYAMA Michitaka TOHOKU UNIVERSITY FACULTY OF ENGINEERING PROFESSOR, 工学部, 教授 (70124568)
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| Project Period (FY) |
1991 – 1992
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| Keywords | 4-Valued CMOS Integrated Circuit / Pattern Matching Cell / Floating-Gate MOS-FET / Inference VLSI Chip / Object Recognition System / Graph Matching / Clique Finding / 3-D Object Recognition |
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| Research Abstract |
This project presents a dynamically rule-programmable, ultra-high-speed inference accelerator VLSI ( called hardware engine ) based on fully parallel
pattern matching. Rules and attributes in the processor are essentially independent of one another, so that pattern matching operations can be performed
in parallel by rules and attributes. Because each attribute is directly encoded by a single multiple-valued digit, one-digit pattern matching can be
easily described by only a 'programmable delta literal'. Moreover, a one-digit pattern matching cell can be simply implemented using a floating-gate MOS
device, where threshold voltages correspond to the content of an attribute value. This property makes rule programming easily in such a pattern matching
cell.
The layout of the proposed inference accelerator VLSI is given by using a 2 mum double-poly double-metal design rule. The effective size of the accelerator chip is about 7.0 x 8.0 ( mm^2 ) including 256 rules, 144 attributes and two types of
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conflict resolution circuit. Because each block in the VLSI processor is executed in parallel, ultra-high-speed inference can be achieved. Using SPICE2 simulation, the inference time is estimated at about 300 ns, which is about 1700 times faster than that of the conventional software-based systems with 32-bit 100 MIPS workstation.
3-D objects are represented by graphs whose vertices and edges correspond to the apexes of objects and the line segments between apexes, respectively. In 3-D object recognition based on graph matching, one of the most important procedures is to find the best available sets ( called 'cliques') of mutually compatible assignments between two graphs, that is, 'clique finding'. As an application, a new highly parallel clique-finding VLSI processor for high-speed graph matching has been shown. The enhanced performance is attributed to the parallel search procedure operated in a digit pipelining and theuse of floating gate MOS devices. The proposed processor will be used in not only 3-D object recognition, but also several applications in fields that have structural data. Less
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