1992 Fiscal Year Final Research Report Summary
Study on Neural Network for Test Generation of Large Scale Logic Circuits
| Project/Area Number |
03650312
|
|---|
| Research Category |
Grant-in-Aid for General Scientific Research (C)
|
| Allocation Type | Single-year Grants |
|---|
| Research Field |
情報工学
|
|---|
| Research Institution | Meiji University |
|---|
Principal Investigator |
FUJIWARA Hideo Meiji University, School of Science and Technology, Professor, 理工学部, 教授 (70029346)
|
|---|
| Project Period (FY) |
1991 – 1992
|
| Keywords | Neural Networks / Logic Circuits / Test Generation / VLSI / Algorithms / Fault Detection |
|---|
| Research Abstract |
With the advent of VLSI and ULSI, the problem of testing logic circuits has become more and more difficult. So, it has become necessary to do research on the acceleration of automatic test generation. In this research project, we have proposed a new approach to accelerate test pattern generation using 3-valued neural networks. We have implemented a test generation system using a neural network simulator and did experiments using ISCAS benchmark circuits. Though it was predicted from the beginning, the experimental results show that the speed of software simulator of neural networks is too slow to accelerate the test pattern generation for large scale logic circuits. Especially, for the problem of test generation, only a vector corresponding to a state of the neural network which minimizes the energy of the network becomes a test pattern for the corresponding circuit. To escape from local minima in the Hopfield model, we adopted the Boltzman model. However, the experimental result shows that it is very hard to converge or find an optimal solution on the Boltzman model. The objective is to find out an approach to parallel processing which accelerates the test pattern generation for large scale logic circuits, so we also did the research on parallel test pattern generation using a network with more than one hundred workstations.
|
